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PIC16F630/676 Data Sheet
14-Pin, Flash-Based 8-Bit CMOS Microcontrollers
(c) 2006 Microchip Technology Inc.
DS40039D
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS40039D-page ii
(c) 2006 Microchip Technology Inc.
PIC16F630/676
14-Pin, Flash-Based 8-Bit CMOS Microcontroller
High Performance RISC CPU:
* Only 35 instructions to learn - All single-cycle instructions except branches * Operating speed: - DC - 20 MHz oscillator/clock input - DC - 200 ns instruction cycle * Interrupt capability * 8-level deep hardware stack * Direct, Indirect, and Relative Addressing modes
Low Power Features:
* Standby Current: - 1 nA @ 2.0V, typical * Operating Current: - 8.5 A @ 32 kHz, 2.0V, typical - 100 A @ 1 MHz, 2.0V, typical * Watchdog Timer Current - 300 nA @ 2.0V, typical * Timer1 oscillator current: - 4 A @ 32 kHz, 2.0V, typical
Special Microcontroller Features:
* Internal and external oscillator options - Precision Internal 4 MHz oscillator factory calibrated to 1% - External Oscillator support for crystals and resonators - 5 s wake-up from SLEEP, 3.0V, typical * Power saving SLEEP mode * Wide operating voltage range - 2.0V to 5.5V * Industrial and Extended temperature range * Low power Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Brown-out Detect (BOD) * Watchdog Timer (WDT) with independent oscillator for reliable operation * Multiplexed MCLR/Input-pin * Interrupt-on-pin change * Individual programmable weak pull-ups * Programmable code protection * High Endurance FLASH/EEPROM Cell - 100,000 write FLASH endurance - 1,000,000 write EEPROM endurance - FLASH/Data EEPROM Retention: > 40 years
Program Memory FLASH (words) 1024 1024 Data Memory SRAM (bytes) 64 64 EEPROM (bytes) 128 128
Peripheral Features:
* 12 I/O pins with individual direction control * High current sink/source for direct LED drive * Analog comparator module with: - One analog comparator - Programmable on-chip comparator voltage reference (CVREF) module - Programmable input multiplexing from device inputs - Comparator output is externally accessible * Analog-to-Digital Converter module (PIC16F676): - 10-bit resolution - Programmable 8-channel input - Voltage reference input * Timer0: 8-bit timer/counter with 8-bit programmable prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator, if INTOSC mode selected * In-Circuit Serial ProgrammingTM (ICSPTM) via two pins
10-bit A/D (ch) - 8 Timers 8/16-bit 1/1 1/1
Device
I/O
Comparators
PIC16F630 PIC16F676
12 12
1 1
(c) 2006 Microchip Technology Inc.
DS40039D-page 1
PIC16F630/676
Pin Diagrams
14-pin PDIP, SOIC, TSSOP
VDD RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5 RC4 RC3
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VSS RA0/CIN+/ICSPDAT RA1/CIN-/ICSPCLK RA2/COUT/T0CKI/INT RC0 RC1 RC2
PIC16F630
VDD RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/AN3/CLKOUT RA3/MCLR/VPP RC5 RC4 RC3/AN7
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VSS RA0/AN0/CIN+/ICSPDAT RA1/AN1/CIN-/VREF/ICSPCLK RA2/AN2/COUT/T0CKI/INT RC0/AN4 RC1/AN5 RC2/AN6
PIC16F676
DS40039D-page 2
(c) 2006 Microchip Technology Inc.
PIC16F630/676
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 5 2.0 Memory Organization .................................................................................................................................................................. 7 3.0 Ports A and C ............................................................................................................................................................................ 19 4.0 Timer0 Module .......................................................................................................................................................................... 29 5.0 Timer1 Module with Gate Control ............................................................................................................................................. 32 6.0 Comparator Module .................................................................................................................................................................. 37 7.0 Analog-to-Digital Converter (A/D) Module (PIC16F676 only) ................................................................................................... 43 8.0 Data EEPROM Memory............................................................................................................................................................ 49 9.0 Special Features of the CPU .................................................................................................................................................... 53 10.0 Instruction Set Summary ........................................................................................................................................................... 71 11.0 Development Support ............................................................................................................................................................... 79 12.0 Electrical Specifications ............................................................................................................................................................ 83 13.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 105 14.0 Packaging Information ............................................................................................................................................................ 115 Appendix A: Data Sheet Revision History ......................................................................................................................................... 119 Appendix B: Device Differences ....................................................................................................................................................... 119 Appendix C: Device Migrations ......................................................................................................................................................... 120 Appendix D: Migrating from other PIC(R) Devices .............................................................................................................................. 120 Index ................................................................................................................................................................................................. 121 On-Line Support ................................................................................................................................................................................ 125 Systems Information and Upgrade Hot Line ..................................................................................................................................... 125 Reader Response ............................................................................................................................................................................. 126 Product Identification System ........................................................................................................................................................... 127
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(c) 2006 Microchip Technology Inc.
DS40039D-page 3
PIC16F630/676
NOTES:
DS40039D-page 4
(c) 2006 Microchip Technology Inc.
PIC16F630/676
1.0 DEVICE OVERVIEW
This document contains device specific information for the PIC16F630/676. Additional information may be found in the PIC(R) Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this Data Sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC16F630 and PIC16F676 devices are covered by this Data Sheet. They are identical, except the PIC16F676 has a 10-bit A/D converter. They come in 14-pin PDIP, SOIC and TSSOP packages. Figure 1-1 shows a block diagram of the PIC16F630/676 devices. Table 1-1 shows the pinout description.
FIGURE 1-1:
PIC16F630/676 BLOCK DIAGRAM
INT Configuration 13 Program Counter FLASH Data Bus 8 PORTA RA0 RA1 RAM 8-Level Stack (13-bit) RA2 RA3 RA4 RA5
1K x 14
Program Memory
64 bytes
File Registers RAM Addr 9 PORTC
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr RC0 RC1 RC2 RC3 RC4 RC5 3 Power-up Timer MUX
FSR reg STATUS reg 8
Instruction Decode & Control Timing Generation
Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Detect 8
ALU
OSC1/CLKIN OSC2/CLKOUT
W reg
Internal Oscillator
T1G T1CKI
Timer0 T0CKI
MCLR VDD
VSS
Timer1
Analog to Digital Converter (PIC16F676 only)
Analog Comparator and reference
EEDATA 8 128 bytes DATA EEPROM EEADDR
CIN- CIN+ COUT VREF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
(c) 2006 Microchip Technology Inc.
DS40039D-page 5
PIC16F630/676
TABLE 1-1: PIC16F630/676 PINOUT DESCRIPTION
Function RA0 AN0 CIN+ ICSPDAT RA1 AN1 CINVREF ICSPCLK RA2 AN2 COUT T0CKI INT RA3 MCLR VPP RA4 T1G AN3 OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN RA5 Input Type TTL AN AN TTL TTL AN AN AN ST ST AN -- ST ST TTL ST HV TTL ST AN3 -- -- TTL Output Type CMOS -- CMOS CMOS -- -- -- -- CMOS -- CMOS -- -- -- -- -- CMOS -- -- XTAL CMOS CMOS -- -- -- CMOS -- CMOS -- CMOS -- CMOS -- CMOS CMOS -- -- Description Bi-directional I/O w/ programmable pull-up and Interrupt-on-change A/D Channel 0 input Comparator input Serial Programming Data I/O Bi-directional I/O w/ programmable pull-up and Interrupt-on-change A/D Channel 1 input Comparator input External Voltage reference Serial Programming Clock Bi-directional I/O w/ programmable pull-up and Interrupt-on-change A/D Channel 2 input Comparator output Timer0 clock input External Interrupt Input port with Interrupt-on-change Master Clear Programming voltage Bi-directional I/O w/ programmable pull-up and Interrupt-on-change Timer1 gate A/D Channel 3 input Crystal/Resonator FOSC/4 output Bi-directional I/O w/ programmable pull-up and Interrupt-on-change Timer1 clock Crystal/Resonator External clock input/RC oscillator connection Bi-directional I/O A/D Channel 4 input Bi-directional I/O A/D Channel 5 input Bi-directional I/O A/D Channel 6 input Bi-directional I/O A/D Channel 7 input Bi-directional I/O Bi-directional I/O Ground reference Positive supply Name RA0/AN0/CIN+/ICSPDAT
RA1/AN1/CIN-/VREF/ ICSPCLK
RA2/AN2/COUT/T0CKI/INT
RA3/MCLR/VPP
RA4/T1G/AN3/OSC2/ CLKOUT
RC0/AN4 RC1/AN5 RC2/AN6 RC3/AN7 RC4 RC5 VSS VDD Legend:
T1CKI ST OSC1 XTAL CLKIN ST RC0 TTL AN4 AN4 RC1 TTL AN5 AN5 RC2 TTL AN6 AN6 RC3 TTL AN7 AN7 RC4 TTL RC5 TTL VSS Power VDD Power Shade = PIC16F676 only TTL = TTL input buffer ST = Schmitt Trigger input buffer
DS40039D-page 6
(c) 2006 Microchip Technology Inc.
PIC16F630/676
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
2.2
Data Memory Organization
The PIC16F630/676 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h - 03FFh) for the PIC16F630/676 devices is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 1K x 14 space. The RESET vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).
The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose registers and the Special Function registers. The Special Function registers are located in the first 32 locations of each bank. Register locations 20h-5Fh are General Purpose registers, implemented as static RAM and are mapped across both banks. All other RAM is unimplemented and returns `0' when read. RP0 (STATUS<5>) is the bank select bit. * RP0 = 0 Bank 0 is selected * RP0 = 1 Bank 1 is selected Note: The IRP and RP1 bits STATUS<7:6> are reserved and should always be maintained as `0's.
FIGURE 2-1:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16F630/676
PC<12:0>
CALL, RETURN RETFIE, RETLW
2.2.1
13
GENERAL PURPOSE REGISTER FILE
Stack Level 1 Stack Level 2 Stack Level 8 RESET Vector 000h
The register file is organized as 64 x 8 in the PIC16F630/676 devices. Each register is accessed, either directly or indirectly, through the File Select Register FSR (see Section 2.4).
Interrupt Vector
0004 0005
On-chip Program Memory 03FFh 0400h
1FFFh
(c) 2006 Microchip Technology Inc.
DS40039D-page 7
PIC16F630/676
2.2.2 SPECIAL FUNCTION REGISTERS FIGURE 2-2:
The Special Function registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function registers associated with the "core" are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
DATA MEMORY MAP OF THE PIC16F630/676
File Address File Address Indirect addr.(1) OPTION_REG PCL STATUS FSR TRISA TRISC 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTC
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h
PCLATH INTCON PIR1 TMR1L TMR1H T1CON
PCLATH INTCON PIE1 PCON OSCCAL ANSEL(2)
WPUA IOCA
CMCON
ADRESH(2) ADCON0(2)
VRCON EEDAT EEADR EECON1 EECON2(1) ADRESL(2) ADCON1(2)
General Purpose Registers 64 Bytes
accesses 20h-5Fh
5Fh 60h
DFh E0h
7Fh Bank 0 Bank 1
FFh
Unimplemented data memory locations, read as '0'. 1: Not a physical register. 2: PIC16F676 only.
DS40039D-page 8
(c) 2006 Microchip Technology Inc.
PIC16F630/676
TABLE 2-1:
Addr
Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: 2: 3: INDF TMR0 PCL STATUS FSR PORTA -- PORTC -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON -- -- -- -- -- -- -- -- CMCON -- -- -- -- ADRESH(3) ADCON0(3) Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP(2) RP1(2) RP0 TO PD Z DC C xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --xx xxxx -- 18,61 29 17 11 18 19 -- 26 -- -- 17 13 15 -- 32 32 34 -- -- -- -- -- -- -- -- 37 -- -- -- -- 44 45,61
PIC16F630/676 SPECIAL REGISTERS SUMMARY BANK 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOD Page
Name
Indirect data memory address pointer
--
Unimplemented
-- --
I/O Control Registers
--
Unimplemented Unimplemented -- GIE EEIF
I/O Control Registers
--xx xxxx -- --
-- PEIE ADIF
-- T0IE --
Write buffer for upper 5 bits of program counter INTE -- RAIE CMIF T0IF -- INTF -- RAIF TMR1IF
---0 0000 0000 0000 00-- 0--0 -- xxxx xxxx xxxx xxxx -000 0000 -- -- -- -- -- -- -- --
Unimplemented Holding register for the Least Significant Byte of the 16-bit TMR1 Holding register for the Most Significant Byte of the 16-bit TMR1 -- T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- COUT -- CINV CIS CM2 CM1 CM0 Unimplemented Unimplemented Unimplemented Unimplemented Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result ADFM VCFG -- CHS2 CHS1 CHS0 GO/DONE ADON
-0-0 0000 -- -- -- -- xxxx xxxx 00-0 0000
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation. IRP & RP1 bits are reserved, always maintain these bits clear. PIC16F676 only.
(c) 2006 Microchip Technology Inc.
DS40039D-page 9
PIC16F630/676
TABLE 2-2:
Addr
Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note 1: 2: 3: IOCA -- -- VRCON EEDAT EEADR EECON1 EECON2 ADRESL(3) ADCON1(3) INDF OPTION_REG PCL STATUS FSR TRISA -- TRISC -- -- PCLATH INTCON PIE1 -- PCON -- OSCCAL ANSEL(3) -- -- -- WPUA CAL5 CAL4 CAL3 ANS5 CAL2 ANS4 CAL1 ANS3 CAL0 ANS2 -- ANS1 -- ANS0 ANS7 ANS6 Unimplemented Unimplemented Unimplemented -- -- Unimplemented Unimplemented VREN -- EEPROM data register -- -- VRR -- VR3 VR2 VR1 VR0 -- -- WPUA5 IOCA5 WPUA4 IOCA4 -- IOCA3 WPUA2 IOCA2 WPUA1 IOCA1 WPUA0 IOCA0 Addressing this location uses contents of FSR to address data memory (not a physical register) RAPU IRP(2) -- Unimplemented -- Unimplemented Unimplemented -- GIE EEIE -- -- PEIE ADIE -- -- T0IE -- -- Write buffer for upper 5 bits of program counter INTE -- -- RAIE CMIE -- T0IF -- -- INTF -- POR RAIF TMR1IE BOD -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 INTEDG RP1(2) -- T0CS RP0 TRISA5 T0SE TO TRISA4 PSA PD TRISA3 PS2 Z TRISA2 PS1 DC TRISA1 PS0 C TRISA0 Program Counter's (PC) Least Significant Byte Indirect data memory address pointer xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx --11 1111 -- --11 1111 -- -- ---0 0000 0000 0000 00-- 0--0 -- ---- --qq -- 1000 00-1111 1111 -- -- -- --11 -111 --00 0000 -- -- 0-0- 0000 0000 0000 0000 0000 ---- x000 ---- ---xxxx xxxx 16 46 -- -- -- 20 21 -- -- 42 49 49 50 49 44 18,61 12,30 17 11 18 19 -- -- -- -- 17 13 14 -- 16
PIC16F630/676 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOD Page
Name
Unimplemented
EEPROM address register -- --
--
WRERR
WREN
WR
RD
EEPROM control register 2 (not a physical register) Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
-- ADCS2 ADCS1 ADCS0 -- -- -- -- -000 ---45,61 - = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation. IRP & RP1 bits are reserved, always maintain these bits clear. PIC16F676 only.
DS40039D-page 10
(c) 2006 Microchip Technology Inc.
PIC16F630/676
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains: * the arithmetic status of the ALU * the RESET status * the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any STATUS bits. For other instructions not affecting any STATUS bits, see the "Instruction Set Summary". Note 1: Bits IRP and RP1 (STATUS<7:6>) are not used by the PIC16F630/676 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
STATUS -- STATUS REGISTER (ADDRESS: 03h OR 83h)
Reserved Reserved IRP bit 7 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7 bit 6 bit 5
IRP: This bit is reserved and should be maintained as `0' RP1: This bit is reserved and should be maintained as `0' RP0: Register Bank Select bit (used for direct addressing) 1 = Bank 1 (80h - FFh) 0 = Bank 0 (00h - 7Fh) TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) For borrow, the polarity is reversed. 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
(c) 2006 Microchip Technology Inc.
DS40039D-page 11
PIC16F630/676
2.2.2.2 OPTION Register
Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting PSA bit to `1' (OPTION<3>). See Section 4.4. The OPTION register is a readable and writable register, which contains various control bits to configure: * * * * TMR0/WDT prescaler External RA2/INT interrupt TMR0 Weak pull-ups on PORTA
REGISTER 2-2:
OPTION_REG -- OPTION REGISTER (ADDRESS: 81h)
R/W-1 RAPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
DS40039D-page 12
(c) 2006 Microchip Technology Inc.
PIC16F630/676
2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts.
REGISTER 2-3:
INTCON -- INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RAIE R/W-0 T0IF R/W-0 INTF R/W-0 RAIF bit 0
bit 7
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RA2/INT External Interrupt Enable bit 1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt RAIE: Port Change Interrupt Enable bit(1) 1 = Enables the PORTA change interrupt 0 = Disables the PORTA change interrupt T0IF: TMR0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RA2/INT External Interrupt Flag bit 1 = The RA2/INT external interrupt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur RAIF: Port Change Interrupt Flag bit 1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software) 0 = None of the PORTA <5:0> pins have changed state Note 1: IOCA register must also be enabled. 2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on RESET and should be initialized before clearing T0IF bit. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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PIC16F630/676
2.2.2.4 PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE1 register contains the interrupt enable bits, as shown in Register 2-4.
REGISTER 2-4:
PIE1 -- PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0 EEIE bit 7 R/W-0 ADIE U-0
--
U-0
--
R/W-0 CMIE
U-0
--
U-0
--
R/W-0 TMR1IE bit 0
bit 7
EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt ADIE: A/D Converter Interrupt Enable bit (PIC16F676 only) 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt Unimplemented: Read as `0' CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt Unimplemented: Read as `0' TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5-4 bit 3
bit 2-1 bit 0
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2.2.2.5 PIR1 Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.
REGISTER 2-5:
PIR1 -- PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
R/W-0 EEIF bit 7 R/W-0 ADIF U-0 -- U-0 -- R/W-0 CMIF U-0 -- U-0 -- R/W-0 TMR1IF bit 0
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started ADIF: A/D Converter Interrupt Flag bit (PIC16F676 only) 1 = The A/D conversion is complete (must be cleared in software) 0 = The A/D conversion is not complete Unimplemented: Read as `0' CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed Unimplemented: Read as `0' TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5-4 bit 3
bit 2-1 bit 0
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2.2.2.6 PCON Register
The Power Control (PCON) register contains flag bits to differentiate between a: * * * * Power-on Reset (POR) Brown-out Detect (BOD) Watchdog Timer Reset (WDT) External MCLR Reset
The PCON Register bits are shown in Register 2-6.
REGISTER 2-6:
PCON -- POWER CONTROL REGISTER (ADDRESS: 8Eh)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-x BOD bit 0
bit 7-2 bit 1
Unimplemented: Read as '0' POR: Power-on Reset STATUS bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOD: Brown-out Detect STATUS bit 1 = No Brown-out Detect occurred 0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 0
2.2.2.7
OSCCAL Register
The Oscillator Calibration register (OSCCAL) is used to calibrate the internal 4 MHz oscillator. It contains 6 bits to adjust the frequency up or down to achieve 4 MHz. The OSCCAL register bits are shown in Register 2-7.
REGISTER 2-7:
OSCCAL -- INTERNAL OSCILLATOR CALIBRATION REGISTER (ADDRESS: 90h)
R/W-1 CAL5 bit 7 R/W-0 CAL4 R/W-0 CAL3 R/W-0 CAL2 R/W-0 CAL1 R/W-0 CAL0 U-0 -- U-0 -- bit 0
bit 7-2
CAL5:CAL0: 6-bit Signed Oscillator Calibration bits 111111 = Maximum frequency 100000 = Center frequency 000000 = Minimum frequency Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 1-0
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2.3 PCL and PCLATH
2.3.2 STACK
The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any RESET, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The PIC16F630/676 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no STATUS bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.
FIGURE 2-3:
PCH 12 PC 5 8 7
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 0 Instruction with PCL as Destination ALU result
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note "Implementing a Table Read" (AN556).
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PIC16F630/676
2.4 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1.
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although STATUS bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-4.
EXAMPLE 2-1:
movlw movwf clrf incf btfss goto
INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
NEXT
CONTINUE
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING PIC16F630/676
Indirect Addressing 0 IRP(1) 7 FSR Register 0
Direct Addressing RP1(1) RP0 6 From Opcode
Bank Select Location Select 00 00h 01 10 11
Bank Select 180h
Location Select
Data Memory
Not Used
7Fh Bank 0 For memory map detail see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. Bank 1 Bank 2 Bank 3
1FFh
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PIC16F630/676
3.0 PORTS A AND C
There are as many as twelve general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Note: Additional information on I/O ports may be found in the PIC(R) Mid-Range Reference Manual, (DS33023) register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Note: The ANSEL (91h) and CMCON (19h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. The ANSEL register is defined for the PIC16F676.
EXAMPLE 3-1:
bcf clrf movlw movwf bsf clrf movlw movwf bcf STATUS,RP0 PORTA 05h CMCON STATUS,RP0 ANSEL 0Ch TRISA STATUS,RP0
INITIALIZING PORTA
;Bank 0 ;Init PORTA ;Set RA<2:0> to ;digital I/O ;Bank 1 ;digital I/O ;Set RA<3:2> as inputs ;and set RA<5:4,1:0> ;as outputs ;Bank 0
3.1
PORTA and the TRISA Registers
PORTA is an 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a Hi-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as `1'. Example 3-1 shows how to initialize PORTA. Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. RA3 reads `0' when MCLREN = 1. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA
3.2
Additional Pin Functions
Every PORTA pin on the PIC16F630/676 has an interrupt-on-change option and every PORTA pin, except RA3, has a weak pull-up option. The next two sections describe these functions.
3.2.1
WEAK PULL-UP
Each of the PORTA pins, except RA3, has an individually configurable weak internal pull-up. Control bits WPUAx enable or disable each pull-up. Refer to Register 3-3. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the RAPU bit (OPTION<7>).
REGISTER 3-1:
PORTA -- PORTA REGISTER (ADDRESS: 05h)
U-0 -- bit 7 U-0 -- R/W-x RA5 R/W-x RA4 R/W-x RA3 R/W-x RA2 R/W-x RA1 R/W-x RA0 bit 0
bit 7-6: bit 5-0:
Unimplemented: Read as '0' PORTA<5:0>: PORTA I/O pin 1 = Port pin is >VIH 0 = Port pin is (c) 2006 Microchip Technology Inc.
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REGISTER 3-2: TRISA -- PORTA TRISTATE REGISTER (ADDRESS: 85h)
U-0 -- bit 7 bit 7-6: bit 5-0: Unimplemented: Read as '0' TRISA<5:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note: Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown TRISA<3> always reads 1. U-0 -- R/W-x TRISA5 R/W-x TRISA4 R-1 TRISA3 R/W-x TRISA2 R/W-x TRISA1 R/W-x TRISA0 bit 0
REGISTER 3-3:
WPUA -- WEAK PULL-UP REGISTER (ADDRESS: 95h)
U-0 -- bit 7 U-0 -- R/W-1 WPUA5 R/W-1 WPUA4 U-0 -- R/W-1 WPUA2 R/W-1 WPUA1 R/W-1 WPUA0 bit 0
bit 7-6 bit 5-4
Unimplemented: Read as `0' WPUA<5:4>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled Unimplemented: Read as `0' WPUA<2:0>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global RAPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0). Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 3 bit 2-0
3.2.2
INTERRUPT-ON-CHANGE
Each of the PORTA pins is individually configurable as an interrupt-on-change pin. Control bits IOCAx enable or disable the interrupt function for each pin. Refer to Register 3-4. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTA. The `mismatch' outputs of the last read are OR'd together to set, the PORTA Change Interrupt flag bit (RAIF) in the INTCON register.
This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTA. This will end the mismatch condition. Clear the flag bit RAIF.
A mismatch condition will continue to set flag bit RAIF. Reading PORTA will end the mismatch condition and allow flag bit RAIF to be cleared. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set.
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REGISTER 3-4: IOCA -- INTERRUPT-ON-CHANGE PORTA REGISTER (ADDRESS: 96h)
U-0 -- bit 7 bit 7-6 bit 5-0 Unimplemented: Read as `0' IOCA<5:0>: Interrupt-on-Change PORTA Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note: Global interrupt enable (GIE) must be enabled for individual interrupts to be recognized. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 IOCA5 R/W-0 IOCA4 R/W-0 IOCA3 R/W-0 IOCA2 R/W-0 IOCA1 R/W-0 IOCA0 bit 0
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3.2.3 PIN DESCRIPTIONS AND DIAGRAMS FIGURE 3-1: BLOCK DIAGRAM OF RA0 AND RA1 PINS
Analog Input Mode D CK Q Q RAPU VDD Weak
Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet.
Data Bus WR WPUA RD WPUA
3.2.3.1
RA0/AN0/CIN+
Figure 3-1 shows the diagram for this pin. The RA0 pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the A/D (PIC16F676 only) * an analog input to the comparator
D WR PORTA CK Q Q
VDD
I/O pin
3.2.3.2
RA1/AN1/CIN-/VREF
WR TRISA RD TRISA RD PORTA
D CK
Q Q Analog Input Mode VSS
Figure 3-1 shows the diagram for this pin. The RA1 pin is configurable to function as one of the following: * * * * as a general purpose I/O an analog input for the A/D (PIC16F676 only) an analog input to the comparator a voltage reference input for the A/D (PIC16F676 only)
D WR IOCA RD IOCA CK
Q Q Q EN Q D EN D
Interrupt-on-Change
RD PORTA To Comparator To A/D Converter
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3.2.3.3 RA2/AN2/T0CKI/INT/COUT 3.2.3.4 RA3/MCLR/VPP
Figure 3-2 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the A/D (PIC16F676 only) a digital output from the comparator the clock input for TMR0 an external edge triggered interrupt Figure 3-3 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: * a general purpose input * as Master Clear Reset
FIGURE 3-3:
Data Bus RESET
BLOCK DIAGRAM OF RA3
MCLRE VSS MCLRE VSS
FIGURE 3-2:
Data Bus WR WPUA RD WPUA D CK Q Q
BLOCK DIAGRAM OF RA2
Analog Input Mode VDD Weak RAPU Analog Input Mode VDD WR IOCA RD IOCA RD TRISA RD PORTA D CK
I/O pin
Q Q Q EN Q D EN D
COUT Enable D WR PORTA CK Q Q COUT 1 0 D WR TRISA RD TRISA RD PORTA D WR IOCA RD IOCA CK Q Q Q CK Q Q
Interrupt-on-Change RD PORTA
I/O pin
VSS Analog Input Mode
D EN
Q
D EN
Interrupt-on-Change RD PORTA
To TMR0 To INT To A/D Converter
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3.2.3.5 RA4/AN3/T1G/OSC2/CLKOUT 3.2.3.6 RA5/T1CKI/OSC1/CLKIN
Figure 3-4 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the A/D (PIC16F676 only) a TMR1 gate input a crystal/resonator connection a clock output Figure 3-5 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: * * * * a general purpose I/O a TMR1 clock input a crystal/resonator connection a clock input
FIGURE 3-5: FIGURE 3-4: BLOCK DIAGRAM OF RA4
Analog Input Mode Data Bus WR WPUA RD WPUA D CK Q Q RAPU Oscillator Circuit OSC1 CLKOUT Enable FOSC/4 D WR PORTA CK Q Q CLKOUT Enable VSS D WR TRISA RD TRISA RD PORTA D WR IOCA RD IOCA CK Q Q Q EN Q D EN D RD IOCA CK Q Q CLKOUT Enable Analog Input Mode INTOSC/ RC/EC(2) 1 0 I/O pin D WR TRISA RD TRISA RD PORTA D WR IOCA CK Q CK Q Q VDD WR PORTA D CK Q Q
BLOCK DIAGRAM OF RA5
INTOSC Mode
CLK(1) Modes VDD Weak
TMR1LPEN(1) VDD Weak
Data Bus WR WPUA RD WPUA
D CK
Q Q RAPU Oscillator Circuit OSC2
VDD
I/O pin
VSS INTOSC Mode (1)
Q Q
D EN
Q
D EN
Interrupt-on-Change
Interrupt-on-Change
RD PORTA RD PORTA To TMR1 or CLKGEN
To TMR1 T1G To A/D Converter Note Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT Enable. 2: With CLKOUT option. 1: Timer1 LP Oscillator enabled. 2: When using Timer1 with LP oscillator, the Schmitt Trigger is by-passed.
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TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on: POR, BOD
--xx xxxx 0000 0000 -0-0 0000 1111 1111 --11 1111 1111 1111 --11 -111 --00 0000
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on all other RESETS
--uu uuuu 0000 000u -0-0 0000 1111 1111 --11 1111 1111 1111 --11 -111 --00 0000
05h 0Bh/8Bh 19h 81h 85h 91h 95h 96h
PORTA INTCON CMCON OPTION_REG TRISA ANSEL(1) WPUA IOCA
-- GIE -- RAPU -- ANS7 -- --
-- PEIE COUT INTEDG -- ANS6 -- --
RA5 T0IE -- T0CS TRISA5 ANS5 WPUA5 IOCA5
RA4 INTE CINV T0SE TRISA4 ANS4 WPUA4 IOCA4
RA3 RAIE CIS PSA TRISA3 ANS3 -- IOCA3
RA2 T0IF CM2 PS2 TRISA2 ANS2 WPUA2 IOCA2
RA1 INTF CM1 PS1 TRISA1 ANS1 WPUA1 IOCA1
RA0 RAIF CM0 PS0 TRISA0 ANS0 WPUA0 IOCA0
Note 1: PIC16F676 only. Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
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3.3 PORTC
3.3.2 RC4 AND RC5
PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to A/D converter. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. Note: The ANSEL register (91h) must be clear to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. The ANSEL register is defined for the PIC16F676. The RC4 and RC5 pins are configurable to function as a general purpose I/Os.
FIGURE 3-7:
Data bus
BLOCK DIAGRAM OF RC4 AND RC5 PINS
D WR PORTC CK
Q Q
VDD
EXAMPLE 3-2:
bcf clrf bsf clrf movlw movwf bcf STATUS,RP0 PORTC STATUS,RP0 ANSEL 0Ch TRISC STATUS,RP0
INITIALIZING PORTC
;Bank 0 ;Init PORTC ;Bank 1 ;digital I/O ;Set RC<3:2> as inputs ;and set RC<5:4,1:0> ;as outputs ;Bank 0
WR TRISC RD TRISC RD PORTC
I/O Pin D CK Q Q VSS
3.3.1
RC0/AN4, RC1/AN5, RC2/AN6, RC3/ AN7
The RC0/RC1/RC2/RC3 pins are configurable to function as one of the following: * a general purpose I/O * an analog input for the A/D Converter (PIC16F676 only)
FIGURE 3-6:
Data bus
BLOCK DIAGRAM OF RC0/RC1/RC2/RC3 PINs
D WR PORTC CK
Q Q
VDD
I/O Pin D WR TRISC RD TRISC RD PORTC CK Q Q Analog Input Mode VSS
To A/D Converter
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REGISTER 3-5: PORTC -- PORTC REGISTER (ADDRESS: 07h)
U-0 -- bit 7 bit 7-6: bit 5-0: Unimplemented: Read as '0' PORTC<5:0>: General Purpose I/O pin 1 = Port pin is >VIH 0 = Port pin is REGISTER 3-6:
TRISC -- PORTC TRISTATE REGISTER (ADDRESS: 87h)
U-0 -- bit 7 U-0 -- R/W-1 TRISC5 R/W-1 TRISC4 R/W-1 TRISC3 R/W-1 TRISC2 R/W-1 TRISC1 R/W-1 TRISC0 bit 0
bit 7-6: bit 5-0:
Unimplemented: Read as '0' TRISC<5:0>: PORTC Tri-State Control bit 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
TABLE 3-2:
Address
07h 87h 91h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7
-- -- ANS7
Bit 6
-- -- ANS6
Bit 5
RC5 TRISC5 ANS5
Bit 4
RC4 TRISC4 ANS4
Bit 3
RC3 TRISC3 ANS3
Bit 2
RC2 TRISC2 ANS2
Bit 1
RC1 TRISC1 ANS1
Bit 0
RC0 TRISC0 ANS0
Value on: POR, BOD
--xx xxxx --11 1111 1111 1111
Value on all other RESETS
--uu uuuu --11 1111 1111 1111
PORTC TRISC ANSEL(1)
Note 1: PIC16F676 only. Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTC.
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NOTES:
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4.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin RA2/T0CKI. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION_REG<4>). Clearing the T0SE bit selects the rising edge. Note: Counter mode has specific external clock requirements. Additional information on these requirements is available in the PIC(R) Mid-Range Reference Manual, (DS33023).
Figure 4-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. Note: Additional information on the Timer0 module is available in the PIC(R) Mid-Range Reference Manual, (DS33023).
4.2
Timer0 Interrupt
4.1
Timer0 Operation
Timer mode is selected by clearing the T0CS bit (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
A Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit. The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit (INTCON<2>) must be cleared in software by the Timer0 module Interrupt Service Routine before reenabling this interrupt. The Timer0 interrupt cannot wake the processor from SLEEP since the timer is shut-off during SLEEP.
FIGURE 4-1:
CLKOUT (= FOSC/4)
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 1 1 SYNC 2 Cycles 0 0 8-bit Prescaler 1 8 Set Flag bit T0IF on Overflow PSA TMR0 8
T0CKI pin T0SE T0CS
PSA
PS0 - PS2 Watchdog Timer
1 WDT Time-out 0
WDTE Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
PSA
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4.3 Using Timer0 with an External Clock
a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and
Note:
The ANSEL (91h) and CMCON (19h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. The ANSEL register is defined for the PIC16F676.
REGISTER 4-1:
OPTION_REG -- OPTION REGISTER (ADDRESS: 81h)
R/W-1 RAPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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4.4 Prescaler
EXAMPLE 4-1:
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer. For simplicity, this counter will be referred to as "prescaler" throughout this Data Sheet. The prescaler assignment is controlled in software by the control bit PSA (OPTION_REG<3>). Clearing the PSA bit will assign the prescaler to Timer0. Prescale values are selectable via the PS2:PS0 bits (OPTION_REG<2:0>). The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1, x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer.
CHANGING PRESCALER (TIMER0WDT)
;Bank 0 ;Clear WDT ;Clear TMR0 and ; prescaler ;Bank 1
bcf STATUS,RP0 clrwdt clrf TMR0 bsf STATUS,RP0
movlw b'00101111' ;Required if desired movwf OPTION_REG ; PS2:PS0 is clrwdt ; 000 or 001 ; movlw b'00101xxx' ;Set postscaler to movwf OPTION_REG ; desired WDT rate bcf STATUS,RP0 ;Bank 0
4.4.1
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 4-1) must be executed when changing the prescaler assignment from Timer0 to WDT.
To change prescaler from the WDT to the TMR0 module, use the sequence shown in Example 4-2. This precaution must be taken even if the WDT is disabled.
EXAMPLE 4-2:
clrwdt bsf movlw
CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and ; postscaler ;Bank 1
STATUS,RP0
movwf bcf
b'xxxx0xxx' ;Select TMR0, ; prescale, and ; clock source OPTION_REG ; STATUS,RP0 ;Bank 0
TABLE 4-1:
Address 01h 0Bh/8Bh 81h 85h Legend:
REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOD Value on all other RESETS
TMR0 INTCON OPTION_REG TRISA
Timer0 Module Register GIE RAPU -- PEIE INTEDG -- T0IE T0CS INTE T0SE RAIE PSA T0IF PS2 INTF PS1 RAIF PS0
xxxx xxxx uuuu uuuu 0000 0000 0000 000u 1111 1111 1111 1111
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
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5.0 TIMER1 MODULE WITH GATE CONTROL
The Timer1 Control register (T1CON), shown in Register 5-1, is used to enable/disable Timer1 and select the various features of the Timer1 module. Note: Additional information on timer modules is available in the PIC(R) Mid-Range Reference Manual, (DS33023).
The PIC16F630/676 devices have a 16-bit timer. Figure 5-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: * * * * * * * * 16-bit timer/counter (TMR1H:TMR1L) Readable and writable Internal or external clock selection Synchronous or asynchronous operation Interrupt on overflow from FFFFh to 0000h Wake-up upon overflow (Asynchronous mode) Optional external enable input (T1G) Optional LP oscillator
FIGURE 5-1:
TIMER1 BLOCK DIAGRAM
TMR1ON TMR1GE TMR1ON TMR1GE T1G
Set Flag bit TMR1IF on Overflow TMR1 0 TMR1H TMR1L 1 LP Oscillator OSC1 FOSC/4 Internal Clock 1 Prescaler 1, 2, 4, 8 0 2 T1CKPS<1:0> TMR1CS T1SYNC
Synchronized Clock Input
Synchronize Detect SLEEP Input
OSC2 INTOSC w/o CLKOUT T1OSCEN LP
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5.1 Timer1 Modes of Operation 5.2 Timer1 Interrupt
Timer1 can operate in one of three modes: * 16-bit timer with prescaler * 16-bit synchronous counter * 16-bit asynchronous counter In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. In Counter and Timer modules, the counter/timer clock can be gated by the T1G input. If an external clock oscillator is needed (and the microcontroller is using the INTOSC w/o CLKOUT), Timer1 can use the LP oscillator as a clock source. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge. The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1<0>) is set. To enable the interrupt on rollover, you must set these bits: * Timer1 interrupt Enable bit (PIE1<0>) * PEIE bit (INTCON<6>) * GIE bit (INTCON<7>). The interrupt is cleared by clearing the TMR1IF in the Interrupt Service Routine. Note: The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts.
5.3
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4, or 8 divisions of the clock input. The T1CKPS bits (T1CON<5:4>) control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.
FIGURE 5-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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REGISTER 5-1: T1CON -- TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as `0' TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if T1G pin is low 0 = Timer1 is on T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1OSO/T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN
bit 5-4
bit 3
bit 2
bit 1
bit 0
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5.4 Timer1 Operation in Asynchronous Counter Mode 5.5 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins OSC1 (input) and OSC2 (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 32 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 9-2 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the system clock is derived from the internal oscillator. As with the system LP oscillator, the user must provide a software time delay to ensure proper oscillator start-up. TRISA5 and TRISA4 bits are set when the Timer1 oscillator is enabled. RA5 and RA4 read as `0' and TRISA5 and TRISA4 bits read as `1'.
If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 5.4.1).
Note:
The ANSEL (91h) and CMCON (19h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. The ANSEL register is defined for the PIC16F676. READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
5.4.1
Note:
Reading TMR1H or TMR1L, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. Examples 12-2 and 12-3 in the PIC(R) Mid-Range MCU Family Reference Manual (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode.
The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.
5.6
Timer1 Operation During SLEEP
Timer1 can only operate during SLEEP when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To setup the timer to wake the device: * Timer1 must be on (T1CON<0>) * TMR1IE bit (PIE1<0>) must be set * PEIE bit (INTCON<6>) must be set The device will wake-up on an overflow. If the GIE bit (INTCON<7>) is set, the device will wake-up and jump to the Interrupt Service Routine on an overflow.
TABLE 5-1:
Address 0Bh/8Bh 0Ch 0Eh 0Fh 10h 8Ch Name INTCON PIR1 TMR1L TMR1H T1CON PIE1
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7 GIE EEIF Bit 6 PEIE ADIF Bit 5 T0IE -- Bit 4 INTE -- Bit 3 RAIE CMIF Bit 2 T0IF -- Bit 1 INTF -- Bit 0 RAIF Value on POR, BOD Value on all other RESETS
0000 0000 0000 000u
TMR1IF 00-- 0--0 00-- 0--0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1IE 00-- 0--0 00-- 0--0
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- EEIE ADIE -- -- CMIE -- --
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
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NOTES:
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PIC16F630/676
6.0 COMPARATOR MODULE
The PIC16F630/676 devices have one analog comparator. The inputs to the comparator are multiplexed with the RA0 and RA1 pins. There is an on-chip Comparator Voltage Reference that can also be applied to an input of the comparator. In addition, RA2 can be configured as the comparator output. The Comparator Control Register (CMCON), shown in Register 6-1, contains the bits to control the comparator.
REGISTER 6-1:
CMCON -- COMPARATOR CONTROL REGISTER (ADDRESS: 19h)
U-0 -- bit 7 R-0 COUT U-0 -- R/W-0 CINV R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit 0
bit 7 bit 6
Unimplemented: Read as `0' COUT: Comparator Output bit When CINV = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CINV = 1: 1 = VIN+ < VIN0 = VIN+ > VINUnimplemented: Read as `0' CINV: Comparator Output Inversion bit 1 = Output inverted 0 = Output not inverted CIS: Comparator Input Switch bit When CM2:CM0 = 110 or 101: 1 = VIN- connects to CIN+ 0 = VIN- connects to CINCM2:CM0: Comparator Mode bits Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 5 bit 4
bit 3
bit 2-0
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6.1 Comparator Operation
TABLE 6-1:
A single comparator is shown in Figure 6-1, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 6-1 represent the uncertainty due to input offsets and response time. Note: To use CIN+ and CIN- pins as analog inputs, the appropriate bits must be programmed in the CMCON (19h) register.
OUTPUT STATE VS. INPUT CONDITIONS
CINV 0 0 1 1 COUT 0 1 1 0
Input Conditions VIN- > VIN+ VIN- < VIN+ VIN- > VIN+ VIN- < VIN+
FIGURE 6-1:
VIN+ VIN-
SINGLE COMPARATOR
+ Output -
The polarity of the comparator output can be inverted by setting the CINV bit (CMCON<4>). Clearing CINV results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 6-1.
VINVIN+
Output
Note:
CINV bit (CMCON<4>) is clear.
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6.2 Comparator Configuration
There are eight modes of operation for the comparator. The CMCON register, shown in Register 6-1, is used to select the mode. Figure 6-2 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for a specified period of time. Refer to the specifications in Section 12.0. Note: Comparator interrupts should be disabled during a Comparator mode change. Otherwise, a false interrupt may occur.
FIGURE 6-2:
CM2:CM0 = 000
COMPARATOR I/O OPERATING MODES
Comparator Off (Lowest power) CM2:CM0 = 111
Comparator Reset (POR Default Value - low power)
RA1/CINRA0/CIN+ RA2/COUT
A A D Off (Read as '0')
RA1/CINRA0/CIN+ RA2/COUT
D D D Off (Read as '0')
Comparator without Output CM2:CM0 = 010
Comparator w/o Output and with Internal Reference CM2:CM0 = 100
RA1/CINRA0/CIN+ RA2/COUT
A A D COUT
RA1/CINRA0/CIN+ RA2/COUT
A D D From CVREF Module COUT
Comparator with Output and Internal Reference CM2:CM0 = 011
Multiplexed Input with Internal Reference and Output CM2:CM0 = 101
RA1/CINRA0/CIN+ RA2/COUT
A D D From CVREF Module COUT
RA1/CINRA0/CIN+ RA2/COUT
A A D From CVREF Module CIS = 0 CIS = 1 COUT
Comparator with Output CM2:CM0 = 001
Multiplexed Input with Internal Reference CM2:CM0 = 110
RA1/CINRA0/CIN+ RA2/COUT
A A D COUT
RA1/CINRA0/CIN+ RA2/COUT
A A D From CVREF Module CIS = 0 CIS = 1 COUT
A = Analog Input, ports always reads `0' D = Digital Input CIS = Comparator Input Switch (CMCON<3>)
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6.3 Analog Input Connection Considerations
range by more than 0.6V in either direction, one of the diodes is forward biased and a latchup may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current.
A simplified circuit for an analog input is shown in Figure 6-3. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this
FIGURE 6-3:
ANALOG INPUT MODE
VDD Rs < 10K AIN VT = 0.6V RIC
VA
CPIN 5 pF
VT = 0.6V
Leakage 500 nA
Legend:
CPIN VT ILEAKAGE RIC RS VA
Vss = Input Capacitance = Threshold Voltage = Leakage Current at the pin due to Various Junctions = Interconnect Resistance = Source Impedance = Analog Voltage The TRISA<2> bit functions as an output enable/ disable for the RA2 pin while the comparator is in an Output mode. Note 1: When reading the PORTA register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input according to the TTL input specification. 2: Analog levels on any pin that is defined as a digital input, may cause the input buffer to consume more current than is specified.
6.4
Comparator Output
The comparator output, COUT, is read through the CMCON register. This bit is read-only. The comparator output may also be directly output to the RA2 pin in three of the eight possible modes, as shown in Figure 6-2. When in one of these modes, the output on RA2 is asynchronous to the internal clock. Figure 6-4 shows the comparator output block diagram.
FIGURE 6-4:
MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM
RA0/CIN+
To RA2/T0CKI pin To Data Bus RD CMCON Q D EN CINV
RA1/CINCVREF
CM2:CM0
Set CMIF bit
Q
D EN RD CMCON RESET
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6.5 Comparator Reference
The following equations determine the output voltages: VRR = 1 (low range): CVREF = (VR3:VR0 / 24) x VDD VRR = 0 (high range): CVREF = (VDD / 4) + (VR3:VR0 x VDD / 32) The comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. The internal reference signal is used for four of the eight Comparator modes. The VRCON register, Register 6-2, controls the voltage reference module shown in Figure 6-5.
6.5.2
VOLTAGE REFERENCE ACCURACY/ERROR
6.5.1
CONFIGURING THE VOLTAGE REFERENCE
The voltage reference can output 32 distinct voltage levels, 16 in a high range and 16 in a low range.
The full range of VSS to VDD cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 6-5) keep CVREF from approaching VSS or VDD. The Voltage Reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the Comparator Voltage Reference can be found in Section 12.0.
FIGURE 6-5:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages 8R R R R R
VDD 8R 16-1 Analog MUX VREN CVREF to Comparator Input VRR
VR3:VR0
6.6
Comparator Response Time
Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is ensured to have a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (Table 12-7).
While the comparator is enabled during SLEEP, an interrupt will wake-up the device. If the device wakes up from SLEEP, the contents of the CMCON and VRCON registers are not affected.
6.8
Effects of a RESET
6.7
Operation During SLEEP
Both the comparator and voltage reference, if enabled before entering SLEEP mode, remain active during SLEEP. This results in higher SLEEP currents than shown in the power-down specifications. The additional current consumed by the comparator and the voltage reference is shown separately in the specifications. To minimize power consumption while in SLEEP mode, turn off the comparator, CM2:CM0 = 111, and voltage reference, VRCON<7> = 0.
A device RESET forces the CMCON and VRCON registers to their RESET states. This forces the comparator module to be in the Comparator Reset mode, CM2:CM0 = 000 and the voltage reference to its off state. Thus, all potential inputs are analog inputs with the comparator and voltage reference disabled to consume the smallest current possible.
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PIC16F630/676
REGISTER 6-2: VRCON -- VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
R/W-0 VREN bit 7 bit 7 VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain Unimplemented: Read as '0' VRR: CVREF Range Selection bit 1 = Low range 0 = High range Unimplemented: Read as '0' VR3:VR0: CVREF value selection 0 VR [3:0] 15 When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 VRR R/W-0 -- R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0
bit 6 bit 5
bit 4 bit 3-0
6.9
Comparator Interrupts
The comparator interrupt flag is set whenever there is a change in the output value of the comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<6>, to determine the actual change that has occurred. The CMIF bit, PIR1<3>, is the comparator interrupt flag. This bit must be reset in software by clearing it to `0'. Since it is also possible to write a '1' to this register, a simulated interrupt may be initiated. The CMIE bit (PIE1<3>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In addition, the GIE bit must also be set. If any of these bits are cleared, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs.
The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON. This will end the mismatch condition. Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. Note: If a change in the CMCON register (COUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR1<3>) interrupt flag may not get set.
TABLE 6-2:
Address 0Bh/8Bh 0Ch 19h 8Ch 85h 99h Legend:
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7 GIE EEIF -- EEIE -- VREN Bit 6 PEIE ADIF COUT ADIE -- -- Bit 5 T0IE -- -- -- TRISA5 VRR Bit 4 INTE -- CINV -- TRISA4 -- Bit 3 RAIE CMIF CIS CMIE TRISA3 VR3 Bit 2 T0IF -- CM2 -- TRISA2 VR2 Bit 1 INTF -- CM1 -- TRISA1 VR1 Bit 0 RAIF Value on POR, BOD Value on all other RESETS
Name INTCON PIR1 CMCON PIE1 TRISA VRCON
0000 0000 0000 000u
TMR1IF 00-- 0--0 00-- 0--0 CM0 -0-0 0000 -0-0 0000
TMR1IE 00-- 0--0 00-- 0--0 TRISA0 VR0 --11 1111 --11 1111 0-0- 0000 0-0- 0000
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the comparator module.
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7.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE (PIC16F676 ONLY)
The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference used in the conversion is software selectable to either VDD or a voltage applied by the VREF pin. Figure 7-1 shows the block diagram of the A/D on the PIC16F676.
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representation of that signal. The PIC16F676 has eight analog inputs, multiplexed into one sample and hold circuit.
FIGURE 7-1:
A/D BLOCK DIAGRAM
VDD
VCFG = 0
VREF
VCFG = 1
RA0/AN0 RA1/AN1/VREF RA2/AN2 RA4/AN3 RC0/AN4 RC1/AN5 RC2/AN6 RC3/AN7 CHS2:CHS0 ADON ADRESH VSS GO/DONE ADFM 10 ADRESL ADC 10
7.1
A/D Configuration and Operation
7.1.3
VOLTAGE REFERENCE
There are three registers available to control the functionality of the A/D module: 1. 2. 3. ADCON0 (Register 7-1) ADCON1 (Register 7-2) ANSEL (Register 7-3)
There are two options for the voltage reference to the A/D converter: either VDD is used, or an analog voltage applied to VREF is used. The VCFG bit (ADCON0<6>) controls the voltage reference selection. If VCFG is set, then the voltage on the VREF pin is the reference; otherwise, VDD is the reference.
7.1.1
ANALOG PORT PINS
7.1.4
CONVERSION CLOCK
The ANS7:ANS0 bits (ANSEL<7:0>) and the TRISA bits control the operation of the A/D port pins. Set the corresponding TRISA bits to set the pin output driver to its high impedance state. Likewise, set the corresponding ANS bit to disable the digital input buffer. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.
The A/D conversion cycle requires 11 TAD. The source of the conversion clock is software selectable via the ADCS bits (ADCON1<6:4>). There are seven possible clock options: * * * * * * * FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator)
7.1.2
CHANNEL SELECTION
There are eight analog channels on the PIC16F676, AN0 through AN7. The CHS2:CHS0 bits (ADCON0<4:2>) control which channel is connected to the sample and hold circuit.
For correct conversion, the A/D conversion clock (1/TAD) must be selected to ensure a minimum TAD of 1.6 s. Table 7-1 shows a few TAD calculations for selected frequencies.
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TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency A/D Clock Source (TAD)
Operation ADCS2:ADCS0 20 MHz 5 MHz 4 MHz 1.25 MHz 2 TOSC 000 100 ns(2) 400 ns(2) 500 ns(2) 1.6 s 4 TOSC 100 200 ns(2) 800 ns(2) 1.0 s(2) 3.2 s 001 400 ns(2) 1.6 s 2.0 s 6.4 s 8 TOSC (2) 16 TOSC 101 800 ns 3.2 s 4.0 s 12.8 s(3) (3) 32 TOSC 010 1.6 s 6.4 s 8.0 s 25.6 s(3) (3) (3) 64 TOSC 110 3.2 s 12.8 s 16.0 s 51.2 s(3) (1,4) (1,4) (1,4) A/D RC x11 2 - 6 s 2 - 6 s 2 - 6 s 2 - 6 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the conversion will be performed during SLEEP.
7.1.5
STARTING A CONVERSION
The A/D conversion is initiated by setting the GO/DONE bit (ADCON0<1>). When the conversion is complete, the A/D module: * Clears the GO/DONE bit * Sets the ADIF flag (PIR1<6>) * Generates an interrupt (if enabled) If the conversion must be aborted, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete A/D conversion sample. Instead, the ADRESH:ADRESL registers will retain the value of the
previous conversion. After an aborted conversion, a 2 TAD delay is required before another acquisition can be initiated. Following the delay, an input acquisition is automatically started on the selected channel. Note: The GO/DONE bit should not be set in the same instruction that turns on the A/D.
7.1.6
CONVERSION OUTPUT
The A/D conversion can be supplied in two formats: left or right shifted. The ADFM bit (ADCON0<7>) controls the output format. Figure 7-2 shows the output formats.
FIGURE 7-2:
10-BIT A/D RESULT FORMAT
ADRESH ADRESL LSB bit 0 bit 7 bit 0
(ADFM = 0)
MSB bit 7
10-bit A/D Result (ADFM = 1) bit 7 MSB bit 0 bit 7
Unimplemented: Read as `0' LSB bit 0
Unimplemented: Read as `0
10-bit A/D Result
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REGISTER 7-1: ADCON0 -- A/D CONTROL REGISTER (ADDRESS: 1Fh)
R/W-0 ADFM bit 7 bit 7 ADFM: A/D Result Formed Select bit 1 = Right justified 0 = Left justified VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD Unimplemented: Read as zero CHS2:CHS0: Analog Channel Select bits 000 =Channel 00 (AN0) 001 =Channel 01 (AN1) 010 =Channel 02 (AN2) 011 =Channel 03 (AN3) 100 =Channel 04 (AN4) 101 =Channel 05 (AN5) 110 =Channel 06 (AN6) 111 =Channel 07 (AN7) GO/DONE: A/D Conversion STATUS bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress ADON: A/D Conversion STATUS bit 1 = A/D converter module is operating 0 = A/D converter is shut-off and consumes no operating current Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 VCFG U-0 -- R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
bit 6
bit 5 bit 4-2
bit 1
bit 0
REGISTER 7-2:
ADCON1 -- A/D CONTROL REGISTER 1 (ADRESS: 9Fh)
U-0 -- bit 7 R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7: bit 6-4:
Unimplemented: Read as `0'. ADCS<2:0>: A/D Conversion Clock Select bits
000 = 001 = 010 = x11 = 100 = 101 = 110 = FOSC/2 FOSC/8 FOSC/32 FRC (clock derived from a dedicated internal oscillator = 500 kHz max) FOSC/4 FOSC/16 FOSC/64
bit 3-0:
Unimplemented: Read as `0'. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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REGISTER 7-3: ANSEL -- ANALOG SELECT REGISTER (ADRESS: 91h) (PIC16F676 ONLY)
R/W-1 ANS7 bit 7 bit 7-0: R/W-1 ANS6 R/W-1 ANS5 R/W-1 ANS4 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0 bit 0
ANS<7:0>: Analog Select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input.(1) 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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7.2 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 7-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 7-3. The maximum recommended impedance for analog sources is 10 k. As the impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 7-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. To calculate the minimum acquisition time, TACQ, see the PIC(R) Mid-Range Reference Manual (DS33023).
EQUATION 7-1:
TACQ
ACQUISITION TIME
= Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = = = = = = = TAMP + TC + TCOFF 2s + TC + [(Temperature -25C)(0.05s/C)] CHOLD (RIC + RSS + RS) In(1/2047) - 120pF (1k + 7k + 10k) In(0.0004885) 16.47s 2s + 16.47s + [(50C -25C)(0.05s/C) 19.72s
TC
TACQ
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
FIGURE 7-3:
ANALOG INPUT MODEL
VDD RS VA ANx CPIN 5 pF VT = 0.6V Sampling Switch RIC 1K SS RSS I LEAKAGE 500 nA CHOLD = DAC capacitance = 120 pF VSS Legend: CPIN = input capacitance VT = threshold voltage I LEAKAGE = leakage current at the pin due to various junctions RIC = interconnect resistance SS = sampling switch CHOLD = sample/hold capacitance (from DAC)
VT = 0.6V
6V 5V VDD 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch (k)
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7.3 A/D Operation During SLEEP
The A/D converter module can operate during SLEEP. This requires the A/D clock source to be set to the internal oscillator. When the RC clock source is selected, the A/D waits one instruction before starting the conversion. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the conversion. When the conversion is complete, the GO/DONE bit is cleared, and the result is loaded into the ADRESH:ADRESL registers. If the A/D interrupt is enabled, the device awakens from SLEEP. If the A/D interrupt is not enabled, the A/D module is turned off, although the ADON bit remains set. When the A/D clock source is something other than RC, a SLEEP instruction causes the present conversion to be aborted, and the A/D module is turned off. The ADON bit remains set.
7.4
Effects of RESET
A device RESET forces all registers to their RESET state. Thus, the A/D module is turned off and any pending conversion is aborted. The ADRESH:ADRESL registers are unchanged.
TABLE 7-2:
Address 05h 07h 0Ch 1Eh 1Fh 85h 87h 8Ch 91h 9Eh 9Fh Name PORTA PORTC PIR1
SUMMARY OF A/D REGISTERS
Bit 7 -- -- GIE EEIF ADFM -- -- EEIE ANS7 -- Bit 6 -- -- PEIE ADIF VCFG -- -- ADIE ANS6 ADCS2 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOD Value on all other RESETS
PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 --xx xxxx --uu uuuu PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 --xx xxxx --uu uuuu T0IE -- -- TRISA5 TRISC5 -- ANS5 ADCS1 INTE -- CHS2 TRISA4 TRISC4 -- ANS4 ADCS0 RAIE CMIF CHS1 TRISA3 TRISC3 CMIE ANS3 -- T0IF -- CHS0 TRISA2 TRISC2 -- ANS2 -- INTF -- GO TRISA1 TRISC1 -- ANS1 -- RAIF 0000 0000 0000 000u TMR1IF 00-- 0--0 00-- 0--0 xxxx xxxx uuuu uuuu 00-0 0000 00-0 0000 ADON
0Bh, 8Bh INTCON
ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result ADCON0 TRISA TRISC PIE1 ANSEL ADCON1
TRISA0 --11 1111 --11 1111 TRISC0 --11 1111 --11 1111 TMR1IE 00-- 0--0 00-- 0--0 ANS0 -- 1111 1111 1111 1111 xxxx xxxx uuuu uuuu -000 ---- -000 ----
ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D converter module.
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8.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory: * * * * EECON1 EECON2 (not a physically implemented register) EEDATA EEADR The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature as well as from chip to chip. Please refer to AC Specifications for exact limits. When the data memory is code protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access this memory. Additional information on the Data EEPROM is available in the PIC(R) Mid-Range Reference Manual, (DS33023).
EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC16F630/676 devices have 128 bytes of data EEPROM with an address range from 0h to 7Fh.
REGISTER 8-1:
EEDAT -- EEPROM DATA REGISTER (ADDRESS: 9Ah)
R/W-0 EEDAT7 bit 7 R/W-0 EEDAT6 R/W-0 EEDAT5 R/W-0 EEDAT4 R/W-0 EEDAT3 R/W-0 R/W-0 R/W-0 EEDAT0 bit 0 EEDAT2 EEDAT1
bit 7-0
EEDATn: Byte value to write to or read from Data EEPROM Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
REGISTER 8-2:
EEADR -- EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)
U-0 -- bit 7 R/W-0 EADR6 R/W-0 EADR5 R/W-0 EADR4 R/W-0 EADR3 R/W-0 EADR2 R/W-0 EADR1 R/W-0 EADR0 bit 0
bit 7 bit 6-0
Unimplemented: Should be set to '0' EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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8.1 EEADR
The EEADR register can address up to a maximum of 128 bytes of data EEPROM. Only seven of the eight bits in the register (EEADR<6:0>) are required. The MSb (bit 7) is ignored. The upper bit should always be `0' to remain upward compatible with devices that have more data EEPROM memory. of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, following RESET, the user can check the WRERR bit, clear it, and rewrite the location. The data and address will be cleared, therefore, the EEDATA and EEADR registers will need to be re-initialized. Interrupt flag bit EEIF in the PIR1 register is set when write is complete. This bit must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is used exclusively in the Data EEPROM write sequence.
8.2
EECON1 AND EECON2 REGISTERS
EECON1 is the control register with four low order bits physically implemented. The upper four bits are nonimplemented and read as '0's. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion
REGISTER 8-3:
EECON1 -- EEPROM CONTROL REGISTER (ADDRESS: 9Ch)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 7-4 bit 3
Unimplemented: Read as `0' WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOD detect) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set, not cleared, in software.) 0 = Does not initiate an EEPROM read Legend: S = Bit can only be set R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 2
bit 1
bit 0
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8.3 READING THE EEPROM DATA MEMORY
After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. The EEIF bit (PIR<7>) register must be cleared by software.
To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>), as shown in Example 8-1. The data is available, in the very next cycle, in the EEDATA register. Therefore, it can be read in the next instruction. EEDATA holds this value until another read, or until it is written to by the user (during a write operation).
8.5
WRITE VERIFY
EXAMPLE 8-1:
bsf movlw movwf bsf movf
DATA EEPROM READ
;Bank 1 ; ;Address to read ;EE Read ;Move data to W
STATUS,RP0 CONFIG_ADDR EEADR EECON1,RD EEDATA,W
Depending on the application, good programming practice may dictate that the value written to the Data EEPROM should be verified (see Example 8-3) to the desired value to be written.
EXAMPLE 8-3:
bcf : bsf movf bsf
WRITE VERIFY
;Bank 0 ;Any code ;Bank 1 READ ;EEDATA not changed ;from previous write ;YES, Read the ;value written ;Is data the same ;No, handle error ;Yes, continue
STATUS,RP0 STATUS,RP0 EEDATA,W EECON1,RD
8.4
WRITING TO THE EEPROM DATA MEMORY
To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDATA register. Then the user must follow a specific sequence to initiate the write for each byte, as shown in Example 8-2.
xorwf EEDATA,W btfss STATUS,Z goto WRITE_ERR :
EXAMPLE 8-2:
bsf bsf bcf movlw movwf movlw movwf bsf bsf
DATA EEPROM WRITE 8.5.1 USING THE DATA EEPROM
;Bank 1 ;Enable write ;Disable INTs ;Unlock write ; ; ; ;Start the write ;Enable INTS
STATUS,RP0 EECON1,WREN INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE
The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. A cycle count is executed during the required sequence. Any number that is not equal to the required cycles to execute the required sequence will prevent the data from being written into the EEPROM. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.
The Data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specifications D120 or D120A. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in FLASH program memory.
Required Sequence
8.6
PROTECTION AGAINST SPURIOUS WRITE
There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: * brown-out * power glitch * software malfunction
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8.7 DATA EEPROM OPERATION DURING CODE PROTECT
Data memory can be code protected by programming the CPD bit to `0'. When the data memory is code protected, the CPU is able to read and write data to the Data EEPROM. It is recommended to code protect the program memory when code protecting data memory. This prevents anyone from programming zeroes over the existing code (which will execute as NOPs) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. Programming unused locations to `0' will also help prevent data memory code protection from becoming breached.
TABLE 8-1:
Address 0Ch 9Ah 9Bh 9Ch 9Dh
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Name Bit 7 EEIF -- -- Bit 6 ADIF Bit 5 -- Bit 4 -- Bit 3 CMIF Bit 2 -- Bit 1 -- Bit 0 Value on POR, BOD Value on all other RESETS
PIR1 EEDATA EEADR EECON1
TMR1IF 00-- 0--0 00-- 0--0 0000 0000 0000 0000 -000 0000 -000 0000
EEPROM Data Register EEPROM Address Register -- -- -- WRERR WREN WR RD
---- x000 ---- q000 ---- ---- ---- ----
EECON2(1) EEPROM Control Register 2
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not used by Data EEPROM module. Note 1: EECON2 is not a physical register.
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9.0 SPECIAL FEATURES OF THE CPU
The PIC16F630/676 has a Watchdog Timer that is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in RESET while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can provide at least a 72 ms RESET. With these three functions on-chip, most applications need no external RESET circuitry. The SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through: * External RESET * Watchdog Timer wake-up * An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options (see Register 9-1).
Certain special circuits that deal with the needs of real time applications are what sets a microcontroller apart from other processors. The PIC16F630/676 family has a host of such features intended to: * maximize system reliability * minimize cost through elimination of external components * provide power saving operating modes and offer code protection These features are: * Oscillator selection * RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Detect (BOD) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code protection * ID Locations * In-Circuit Serial Programming
(c) 2006 Microchip Technology Inc.
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PIC16F630/676
9.1 Configuration Bits
Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h - 3FFFh), which can be accessed only during programming. See PIC16F630/676 Programming Specification for more information. The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1') to select various device configurations, as shown in Register 9-1. These bits are mapped in program memory location 2007h.
REGISTER 9-1:
R/P-1 R/P-1 BG1 bit 13 BG0 U-0 --
CONFIG -- CONFIGURATION WORD (ADDRESS: 2007h)
U-0 -- U-0 -- R/P-1 CPD R/P-1 CP R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 bit 0
bit 13-12
bit 11-9 bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
BG1:BG0: Bandgap Calibration bits for BOD and POR voltage(1) 00 = Lowest bandgap voltage 11 = Highest bandgap voltage Unimplemented: Read as `0' CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled CP: Code Protection bit(3) 1 = Program Memory code protection is disabled 0 = Program Memory code protection is enabled BODEN: Brown-out Detect Enable bit(4) 1 = BOD enabled 0 = BOD disabled MCLRE: RA3/MCLR pin function select(5) 1 = RA3/MCLR pin function is MCLR 0 = RA3/MCLR pin function is digital I/O, MCLR internally tied to VDD PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC2:FOSC0: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN 110 = RC oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 100 = INTOSC oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 011 = EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN 010 = HS oscillator: High speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 000 = LP oscillator: Low power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing the device as specified in the PIC16F630/676 Programming Specification. These bits are reflected in an export of the configuration word. Microchip Development Tools maintain all calibration bits to factory settings. 2: The entire data EEPROM will be erased when the code protection is turned off. 3: The entire program memory will be erased, including OSCCAL value, when the code protection is turned off. 4: Enabling Brown-out Detect does not automatically enable Power-up Timer. 5: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. Legend: P = Programmed using ICSP R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
(c) 2006 Microchip Technology Inc.
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9.2
9.2.1
Oscillator Configurations
OSCILLATOR TYPES
FIGURE 9-2:
The PIC16F630/676 can be operated in eight different Oscillator Option modes. The user can program three configuration bits (FOSC2 through FOSC0) to select one of these eight modes: * * * * * * LP Low Power Crystal XT Crystal/Resonator HS High Speed Crystal/Resonator RC External Resistor/Capacitor (2 modes) INTOSC Internal Oscillator (2 modes) EC External Clock In Note: Additional information on oscillator configurations is available in the PIC(R) Mid-Range Reference Manual, (DS33023).
EXTERNAL CLOCK INPUT OPERATION (HS, XT, EC, OR LP OSC CONFIGURATION)
Clock from External System
OSC1 PIC16F630/676
Open
OSC2(1)
Note 1: Functions as RA4 in EC Osc mode.
TABLE 9-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS
Ranges Characterized:
Mode XT
Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz
OSC1(C1) 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
OSC2(C2) 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
9.2.2
CRYSTAL OSCILLATOR / CERAMIC RESONATORS
In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (see Figure 9-1). The PIC16F630/676 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may yield a frequency outside of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1 pin (see Figure 9-2).
HS
FIGURE 9-1:
CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)
OSC1 To Internal Logic XTAL OSC2 RF(3) SLEEP
Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.
TABLE 9-2:
Mode LP XT
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Freq OSC1(C1) 68 - 100 pF 68 - 150 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF OSC2(C2) 68 - 100 pF 150 - 200 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF
C1(1)
32 kHz 100 kHz 2 MHz 4 MHz 8 MHz 10 MHz 20 MHz
C2(1) Note 1: 2: 3:
RS(2) PIC16F630/676
HS
See Table 9-1 and Table 9-2 for recommended values of C1 and C2. A series resistor may be required for AT strip cut crystals. RF varies with the Oscillator mode selected (Approx. value = 10 M).
Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
(c) 2006 Microchip Technology Inc.
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PIC16F630/676
9.2.3 EXTERNAL CLOCK IN 9.2.5 INTERNAL 4 MHZ OSCILLATOR
For applications where a clock is already available elsewhere, users may directly drive the PIC16F630/ 676 provided that this external clock source meets the AC/DC timing requirements listed in Section 12.0. Figure 9-2 shows how an external clock circuit should be configured. When calibrated, the internal oscillator provides a fixed 4 MHz (nominal) system clock. See Electrical Specifications, Section 12.0, for information on variation over voltage and temperature. Two options are available for this Oscillator mode which allow RA4 to be used as a general purpose I/O or to output FOSC/4.
9.2.4
RC OSCILLATOR
For applications where precise timing is not a requirement, the RC oscillator option is available. The operation and functionality of the RC oscillator is dependent upon a number of variables. The RC oscillator frequency is a function of: * Supply voltage * Resistor (REXT) and capacitor (CEXT) values * Operating temperature The oscillator frequency will vary from unit to unit due to normal process parameter variation. The difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to account for the tolerance of the external R and C components. Figure 9-3 shows how the R/C combination is connected. Two options are available for this Oscillator mode which allow RA4 to be used as a general purpose I/O or to output FOSC/4.
9.2.5.1
Calibrating the Internal Oscillator
A calibration instruction is programmed into the last location of program memory. This instruction is a RETLW XX, where the literal is the calibration value. The literal is placed in the OSCCAL register to set the calibration of the internal oscillator. Example 9-1 demonstrates how to calibrate the internal oscillator. For best operation, decouple (with capacitance) VDD and VSS as close to the device as possible. Note: Erasing the device will also erase the preprogrammed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing part as specified in the PIC16F630/676 Programming specification. Microchip Development Tools maintain all calibration bits to factory settings.
EXAMPLE 9-1:
bsf call movwf bcf
CALIBRATING THE INTERNAL OSCILLATOR
;Bank 1 ;Get the cal value ;Calibrate ;Bank 0
FIGURE 9-3:
VDD
RC OSCILLATOR MODE
STATUS, RP0 3FFh OSCCAL STATUS, RP0
PIC16F630/676
REXT
RA5/OSC1/ CLKIN
Internal Clock
9.2.6
CLKOUT
CEXT VSS FOSC/4 RA4/OSC2/CLKOUT
The PIC16F630/676 devices can be configured to provide a clock out signal in the INTOSC and RC Oscillator modes. When configured, the oscillator frequency divided by four (FOSC/4) is output on the RA4/OSC2/CLKOUT pin. FOSC/4 can be used for test purposes or to synchronize other logic.
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9.3 RESET
The PIC16F630/676 differentiates between various kinds of RESET: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during SLEEP MCLR Reset during normal operation MCLR Reset during SLEEP Brown-out Detect (BOD) They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different RESET situations as indicated in Table 9-4. These bits are used in software to determine the nature of the RESET. See Table 9-7 for a full description of RESET states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 9-4. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Table 12-4 in Electrical Specifications Section for pulse width specification.
Some registers are not affected in any RESET condition; their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a "RESET state" on: * * * * * Power-on Reset MCLR Reset WDT Reset WDT Reset during SLEEP Brown-out Detect (BOD)
FIGURE 9-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR/ VPP pin WDT Module VDD Rise Detect VDD Brown-out Detect WDT
SLEEP
Time-out Reset
Power-on Reset S
BODEN OST/PWRT OST 10-bit Ripple Counter OSC1/ CLKIN pin PWRT On-chip(1) RC OSC 10-bit Ripple Counter
Q
Chip_Reset R Q
Enable PWRT Enable OST
See Table 9-3 for time-out situations.
Note
1:
This is a separate oscillator from the INTOSC/EC oscillator.
(c) 2006 Microchip Technology Inc.
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PIC16F630/676
9.3.1
MCLR PIC16F630/676 devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 9-5, is suggested. An internal MCLR option is enabled by setting the MCLRE bit in the configuration word. When enabled, MCLR is internally tied to VDD. No internal pull-up option is available for the MCLR pin. For additional information, refer to Application Note AN607 "Power-up Trouble Shooting".
9.3.3
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal) time-out on power-up only, from POR or Brown-out Detect. The Power-up Timer operates on an internal RC oscillator. The chip is kept in RESET as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A configuration bit, PWRTE can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should always be enabled when Brown-out Detect is enabled. The Power-up Time delay will vary from chip to chip and due to: * VDD variation * Temperature variation * Process variation. See DC parameters for details (Section 12.0).
FIGURE 9-5:
VDD
RECOMMENDED MCLR CIRCUIT
PIC16F630/676
9.3.4
OSCILLATOR START-UP TIMER (OST)
R1 1 k (or greater) MCLR
The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.
C1 0.1 f (optional, not critical)
9.3.2
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in RESET until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply tie the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Electrical Specifications for details (see Section 12.0). If the BOD is enabled, the maximum rise time specification does not apply. The BOD circuitry will keep the device in RESET until VDD reaches VBOD (see Section 9.3.5). Note: The POR circuit does not produce an internal RESET when VDD declines.
When the device starts normal operation (exits the RESET condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met.
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PIC16F630/676
9.3.5 BROWN-OUT DETECT (BOD)
The PIC16F630/676 members have on-chip Brown-out Detect circuitry. A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Detect circuitry. If VDD falls below VBOD for greater than parameter (TBOD) in Table 12-4 (see Section 12.0), the Brown-out situation will reset the device. This will occur regardless of VDD slew-rate. A RESET is not guaranteed to occur if VDD falls below VBOD for less than parameter (TBOD). On any RESET (Power-on, Brown-out Detect, Watchdog, etc.), the chip will remain in RESET until VDD rises above BVDD (see Figure 9-6). The Power-up Timer will now be invoked, if enabled, and will keep the chip in RESET an additional 72 ms. Note: A Brown-out Detect does not enable the Power-up Timer if the PWRTE bit in the configuration word is set.
If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Detect and the Power-up Timer will be re-initialized. Once VDD rises above BVDD, the Power-up Timer will execute a 72 ms RESET.
FIGURE 9-6:
VDD
BROWN-OUT SITUATIONS
VBOD
Internal RESET
72 ms(1)
VDD VBOD
Internal RESET
<72 ms
72 ms(1)
VDD
VBOD
Internal RESET
72 ms(1)
Note 1: 72 ms delay only if PWRTE bit is programmed to `0'.
9.3.6
TIME-OUT SEQUENCE
9.3.7
On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired. Then, OST is activated. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 9-7, Figure 9-8 and Figure 9-9 depict timeout sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (see Figure 9-8). This is useful for testing purposes or to synchronize more than one PIC16F630/676 device operating in parallel. Table 9-6 shows the RESET conditions for some special registers, while Table 9-7 shows the RESET conditions for all the registers.
POWER CONTROL (PCON) STATUS REGISTER
register, PCON
The power CONTROL/STATUS (address 8Eh) has two bits.
Bit0 is BOD (Brown-out). BOD is unknown on Poweron Reset. It must then be set by the user and checked on subsequent RESETS to see if BOD = 0, indicating that a brown-out has occurred. The BOD STATUS bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by setting BODEN bit = 0 in the Configuration word). Bit1 is POR (Power-on Reset). It is a `0' on Power-on Reset and unaffected otherwise. The user must write a `1' to this bit following a Power-on Reset. On a subsequent RESET, if POR is `0', it will indicate that a Power-on Reset must have occurred (i.e., VDD may have gone too low).
(c) 2006 Microchip Technology Inc.
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PIC16F630/676
TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up Oscillator Configuration PWRTE = 0 XT, HS, LP RC, EC, INTOSC TPWRT + 1024*TOSC TPWRT PWRTE = 1 1024*TOSC -- PWRTE = 0 TPWRT + 1024*TOSC TPWRT PWRTE = 1 1024*TOSC -- Brown-out Detect Wake-up from SLEEP 1024*TOSC --
TABLE 9-4:
POR 0 1 u u u u
STATUS/PCON BITS AND THEIR SIGNIFICANCE
BOD u 0 u u u u TO 1 1 0 0 u 1 PD 1 1 u 0 u 0 Power-on Reset Brown-out Detect WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP
Legend: u = unchanged, x = unknown
TABLE 9-5:
Address 03h 8Eh
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Bit 7 IRP -- Bit 6 RP1 -- Bit 5 RPO -- Bit 4 TO -- Bit 3 PD -- Bit 2 Z -- Bit 1 DC POR Bit 0 C BOD Value on POR, BOD Value on all other RESETS(1)
Name STATUS PCON
0001 1xxx 000q quuu ---- --0x ---- --uq
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
TABLE 9-6:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1
(1)
STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 0001 1uuu uuu1 0uuu
PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu
Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Detect Interrupt Wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1.
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PIC16F630/676
TABLE 9-7:
Register
INITIALIZATION CONDITION FOR REGISTERS
Address Power-on Reset xxxx xxxx -- xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --xx xxxx --xx xxxx ---0 0000 0000 0000 00-- 0--0 -000 0000 -0-0 0000 xxxx xxxx 00-0 0000 1111 1111 --11 1111 --11 1111 00-- 0--0 ---- --0x 1000 00-1111 1111 --11 -111 --00 0000 0-0- 0000 0000 0000 -000 0000 ---- x000 ---- ---xxxx xxxx -000 ---* MCLR Reset * WDT Reset * Brown-out Detect(1) uuuu uuuu -- uuuu uuuu 0000 0000 000q quuu(4) uuuu uuuu --uu uuuu --uu uuuu ---0 0000 0000 000u 00-- 0--0 -uuu uuuu -0-0 0000 uuuu uuuu 00-0 0000 1111 1111 --11 1111 --11 1111 00-- 0--0 ---- --uu(1,6) 1000 00-1111 1111 --11 -111 --00 0000 0-0- 0000 0000 0000 -000 0000 ---- q000 ---- ---uuuu uuuu -000 ---* Wake-up from SLEEP through interrupt * Wake-up from SLEEP through WDT time-out uuuu uuuu -- uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu --uu uuuu --uu uuuu ---u uuuu uuuu uuqq(2) qq-- q--q(2,5) -uuu uuuu -u-u uuuu uuuu uuuu uu-u uuuu uuuu uuuu --uu uuuu --uu uuuu uu-- u--u ---- --uu uuuu uu-uuuu uuuu uuuu uuuu --uu uuuu u-u- uuuu uuuu uuuu -uuu uuuu ---- uuuu ---- ---uuuu uuuu -uuu ----
W INDF TMR0 PCL STATUS FSR PORTA PORTC PCLATH INTCON PIR1 T1CON CMCON ADRESH ADCON0 OPTION_REG TRISA TRISC PIE1 PCON OSCCAL ANSEL WPUA IOCA VRCON EEDATA EEADR EECON1 EECON2 ADRESL ADCON1
-- 00h/80h 01h 02h/82h 03h/83h 04h/84h 05h 07h 0Ah/8Ah 0Bh/8Bh 0Ch 10h 19h 1Eh 1Fh 81h 85h 87h 8Ch 8Eh 90h 91h 95h 96h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 9-6 for RESET value for specific condition. 5: If wake-up was due to data EEPROM write completing, bit 7 = 1; A/D conversion completing, bit 6 = 1; Comparator input changing, bit 3 = 1; or Timer1 rolling over, bit 0 = 1. All other interrupts generating a wake-up will cause these bits to = u. 6: If RESET was due to brown-out, then bit 0 = 0. All other RESETS will cause bit 0 = u.
(c) 2006 Microchip Technology Inc.
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PIC16F630/676
FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal RESET
FIGURE 9-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal RESET
FIGURE 9-9:
VDD MCLR Internal POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
TPWRT PWRT Time-out
TOST
OST Time-out
Internal RESET
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PIC16F630/676
9.4
* * * * * * *
Interrupts
The PIC16F630/676 has 7 sources of interrupt: External Interrupt RA2/INT TMR0 Overflow Interrupt PORTA Change Interrupts Comparator Interrupt A/D Interrupt (PIC16F676 only) TMR1 Overflow Interrupt EEPROM Data Write Interrupt
interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again.
The Interrupt Control register (INTCON) and Peripheral Interrupt register (PIR) record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register and PIE register. GIE is cleared on RESET. The return from interrupt instruction, RETFIE, exits interrupt routine, as well as sets the GIE bit, which reenables unmasked interrupts. The following interrupt flags are contained in the INTCON register: * INT pin interrupt * PORTA change interrupt * TMR0 overflow interrupt The peripheral interrupt flags are contained in the special register PIR1. The corresponding interrupt enable bit is contained in Special Register PIE1. The following interrupt flags are contained in the PIR register: * * * * EEPROM data write interrupt A/D interrupt Comparator interrupt Timer1 overflow interrupt
When an interrupt is serviced: * The GIE is cleared to disable any further interrupt * The return address is pushed onto the stack * The PC is loaded with 0004h Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid RA2/INT recursive interrupts. For external interrupt events, such as the INT pin, or PORTA change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 9-11). The latency is the same for one or twocycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The
(c) 2006 Microchip Technology Inc.
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PIC16F630/676
FIGURE 9-10:
IOCA-RA0 IOCA0 IOCA-RA1 IOCA1 IOCA-RA2 IOCA2 IOCA-RA3 IOCA3 IOCA-RA4 IOCA4 IOCA-RA5 IOCA5 T0IF T0IE INTF INTE RAIF RAIE PEIE
(1)
INTERRUPT LOGIC
Wake-up (If in SLEEP mode)
TMR1IF TMR1IE CMIF CMIE ADIF ADIE EEIF EEIE Note 1: PIC16F676 only.
Interrupt to CPU
GIE
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PIC16F630/676
9.4.1 RA2/INT INTERRUPT 9.4.2 TMR0 INTERRUPT
External interrupt on RA2/INT pin is edge-triggered; either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RA2/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The RA2/INT interrupt can wake-up the processor from SLEEP if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up. See Section 9.7 for details on SLEEP and Figure 9-13 for timing of wake-up from SLEEP through RA2/INT interrupt. An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 4.0.
9.4.3
PORTA INTERRUPT
An input change on PORTA change sets the RAIF (INTCON<0>) bit. The interrupt can be enabled/ disabled by setting/clearing the RAIE (INTCON<3>) bit. Plus individual pins can be configured through the IOCA register. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set.
Note:
The ANSEL (91h) and CMCON (19h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. The ANSEL register is defined for the PIC16F676.
9.4.4
COMPARATOR INTERRUPT
See Section 6.9 for description of comparator interrupt.
9.4.5
A/D CONVERTER INTERRUPT
After a conversion is complete, the ADIF flag (PIR<6>) is set. The interrupt can be enabled/disabled by setting or clearing ADIE (PIE<6>). See Section 7.0 for operation of the A/D converter interrupt.
FIGURE 9-11:
Q1 OSC1 CLKOUT 3 INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed
INT PIN INTERRUPT TIMING
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
4 1 5 Interrupt Latency 2
1
PC
PC+1 Inst (PC+1) Inst (PC)
PC+1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
Inst (PC) Inst (PC-1)
Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC Oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set any time during the Q4-Q1 cycles.
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TABLE 9-8:
Address Name
SUMMARY OF INTERRUPT REGISTERS
Bit 7 GIE EEIF EEIE Bit 6 PEIE ADIF ADIE Bit 5 T0IE -- -- Bit 4 INTE -- -- Bit 3 RAIE CMIF CMIE Bit 2 T0IF -- -- Bit 1 INTF -- -- Bit 0 RAIF Value on POR, BOD Value on all other RESETS
0Bh, 8Bh INTCON 0Ch 8Ch PIR1 PIE1
0000 0000 0000 000u
TMR1IF 00-- 0--0 00-- 0--0 TMR1IE 00-- 0--0 00-- 0--0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not used by the Interrupt module.
9.5
Context Saving During Interrupts
9.6
Watchdog Timer (WDT)
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W register and STATUS register). This must be implemented in software. Example 9-2 stores and restores the STATUS and W registers. The user register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., W_TEMP is defined at 0x20 in Bank 0 and it must also be defined at 0xA0 in Bank 1). The user register, STATUS_TEMP, must be defined in Bank 0. The Example 9-2: * * * * Stores the W register Stores the STATUS register in Bank 0 Executes the ISR code Restores the STATUS (and bank select bit register) * Restores the W register
The Watchdog Timer is a free running, on-chip RC oscillator, which requires no external components. This RC oscillator is separate from the external RC oscillator of the CLKIN pin. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped (for example, by execution of a SLEEP instruction). During normal operation, a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming the configuration bit WDTE as clear (Section 9.1).
9.6.1
WDT PERIOD
EXAMPLE 9-2:
MOVWF SWAPF BCF W_TEMP STATUS,W STATUS,RP0
SAVING THE STATUS AND W REGISTERS IN RAM
;copy W to temp register, could be in either bank ;swap status to be saved into W ;change to bank 0 regardless of current bank ;save status to bank 0 register
The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the prescaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out.
MOVWF STATUS_TEMP : :(ISR) : SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into W, sets bank to original state MOVWF STATUS ;move W into STATUS register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W
9.6.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken in account that under worst case conditions (i.e., VDD = Min., Temperature = Max., Max. WDT prescaler) it may take several seconds before a WDT time-out occurs.
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PIC16F630/676
FIGURE 9-12:
CLKOUT (= FOSC/4) 0 1 1 T0CKI pin T0SE T0CS 1 8 0 8-bit Prescaler 0 Set Flag bit T0IF on Overflow PSA SYNC 2 Cycles TMR0
WATCHDOG TIMER BLOCK DIAGRAM
Data Bus 8
PSA
PS0 - PS2 Watchdog Timer
1 WDT Time-out 0
WDTE
PSA
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
TABLE 9-9:
Address
SUMMARY OF WATCHDOG TIMER REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOD Value on all other RESETS
81h 2007h
OPTION_REG RAPU INTEDG Config. bits CP
T0CS
T0SE
PSA
PS2 F0SC2
PS1 F0SC1
PS0 F0SC0
1111 1111 1111 1111 uuuu uuuu uuuu uuuu
BODEN MCLRE PWRTE WDTE
Legend: u = Unchanged, shaded cells are not used by the Watchdog Timer.
(c) 2006 Microchip Technology Inc.
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9.7 Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: * * * * * WDT will be cleared but keeps running PD bit in the STATUS register is cleared TO bit is set Oscillator driver is turned off I/O ports maintain the status they had before SLEEP was executed (driving high, low, or hi-impedance). The first event will cause a device RESET. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. TO bit is cleared if WDT Wake-up occurred. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have an NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from SLEEP. The SLEEP instruction is completely executed.
For lowest current consumption in this mode, all I/O pins should be either at VDD, or VSS, with no external circuitry drawing current from the I/O pin and the comparators and CVREF should be disabled. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTA should be considered. The MCLR pin must be at a logic high level (VIHMC). Note: It should be noted that a RESET generated by a WDT time-out does not drive MCLR pin low.
The WDT is cleared when the device wakes up from SLEEP, regardless of the source of wake-up.
9.7.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin Watchdog Timer Wake-up (if WDT was enabled) Interrupt from RA2/INT pin, PORTA change, or a peripheral interrupt.
FIGURE 9-13:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: Inst(PC) = SLEEP Inst(PC - 1) Processor in SLEEP
Interrupt Latency (Note 3)
PC+1 Inst(PC + 1) SLEEP
PC+2
PC+2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Dummy cycle
Dummy cycle
XT, HS or LP Oscillator mode assumed. TOST = 1024TOSC (drawing not to scale). Approximately 1 s delay for RC Oscillator mode. See Section 12 for wake-up from SLEEP delay in INTOSC mode. GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in XT, HS, LP or EC Osc modes, but shown here for timing reference.
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9.8 Code Protection
FIGURE 9-14:
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: The entire data EEPROM and FLASH program memory will be erased when the code protection is turned off. The INTOSC calibration data is also erased. See PIC16F630/676 Programming Specification for more information.
External Connector Signals +5V 0V VPP
TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections PIC16F630/676
VDD VSS RA3/MCLR/VPP RA1 RA0
9.9
ID Locations
CLK Data I/O
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify. Only the Least Significant 7 bits of the ID locations are used.
VDD
To Normal Connections
9.10
In-Circuit Serial Programming 9.11 In-Circuit Debugger
The PIC16F630/676 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for: * power * ground * programming voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the RA0 and RA1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH (see Programming Specification). RA0 becomes the programming data and RA1 becomes the programming clock. Both RA0 and RA1 are Schmitt Trigger inputs in this mode. After RESET, to place the device into Programming/ Verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending on whether the command was a load or a read. For complete details of serial programming, please refer to the PIC16F630/676 Programming Specification. A typical In-Circuit Serial Programming connection is shown in Figure 9-14.
Since in-circuit debugging requires the loss of clock, data and MCLR pins, MPLAB(R) ICD 2 development with an 14-pin device is not practical. A special 20-pin PIC16F676-ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user. This special ICD device is mounted on the top of the header and its signals are routed to the MPLAB ICD 2 connector. On the bottom of the header is an 14-pin socket that plugs into the user's target via the 14-pin stand-off connector. When the ICD pin on the PIC16F676-ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 9-10 shows which features are consumed by the background debugger:
TABLE 9-10:
I/O pins Stack
DEBUGGER RESOURCES
ICDCLK, ICDDATA 1 level Address 0h must be NOP 300h - 3FEh
Program Memory
For more information, see 14-Pin MPLAB ICD 2 Header Information Sheet (DS51299) available on Microchip's website (www.microchip.com).
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NOTES:
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10.0 INSTRUCTION SET SUMMARY
The PIC16F630/676 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 10-1, while the various opcode fields are summarized in Table 10-1. Table 10-2 lists the instructions recognized by the MPASMTM assembler. A complete description of each instruction is also available in the PIC(R) Mid-Range Reference Manual (DS33023). For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an 8-bit or 11-bit constant, or literal value One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. Note: To maintain upward compatibility with future products, do not use the OPTION and TRIS instructions. Field
f W b k x
For example, a CLRF PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended result of clearing the condition that set the RAIF flag.
TABLE 10-1:
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Power-down bit
d
PC TO PD
FIGURE 10-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
0
All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
0
10.1
READ-MODIFY-WRITE OPERATIONS
0
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register.
(c) 2006 Microchip Technology Inc.
k = 11-bit immediate value
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TABLE 10-2:
Mnemonic, Operands
PIC16F630/676 INSTRUCTION SET
14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z Z Z Z Z Z Z Z Z
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW f, b f, b f, b f, b k k k k k k k k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 11 11 10 00 10 11 11 00 11 00 00 11 11 00bb 01bb 10bb 11bb 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 bfff bfff bfff bfff kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk ffff ffff ffff ffff kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS
TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PIC(R) Mid-Range MCU Family Reference Manual (DS33023).
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10.2
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add Literal and W [label] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal 'k' and the result is placed in the W register. Operation: Status Affected: Description: k BCF Syntax: Operands: Bit Clear f [label] BCF 0 f 127 0b7 0 (f) None Bit 'b' in register 'f' is cleared. f,b
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [label] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [label] BSF 0 f 127 0b7 1 (f) None Bit 'b' in register 'f' is set. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND Literal with W [label] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal 'k'. The result is placed in the W register. k
BTFSS Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Set [label] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit 'b' in register 'f' is '0', the next instruction is executed. If bit 'b' is '1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [label] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. f,d
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test, Skip if Clear [label] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit 'b' in register 'f' is '1', the next instruction is executed. If bit 'b', in register 'f', is '0', the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction.
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CALL Syntax: Operands: Operation: Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. STATUS bits TO and PD are set.
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [label] CLRF 0 f 127 00h (f) 1Z Z The contents of register 'f' are cleared and the Z bit is set. f
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register 'f' are complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f'. f,d
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [label] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
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DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register 'f' are decremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. If the result is 1, the next instruction is executed. If the result is 0, then a NOP is executed instead, making it a 2-cycle instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register 'f' are incremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead, making it a 2-cycle instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a twocycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal 'k'. The result is placed in the W register.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register 'f' are incremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register 'f'. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
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MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (destination) Z The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag Z is affected. NOP Syntax: Operands: Operation: Status Affected: Description: No Operation [ label ] None No operation None No operation. NOP
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move Literal to W [ label ] k (W) None The eight-bit literal 'k' is loaded into W register. The don't cares will assemble as 0's. MOVLW k 0 k 255
RETFIE Syntax: Operands: Operation: Status Affected:
Return from Interrupt [ label ] None TOS PC, 1 GIE None RETFIE
MOVWF Syntax: Operands: Operation: Status Affected: Description:
Move W to f [ label ] (W) (f) None Move data from W register to register 'f'. MOVWF f 0 f 127
RETLW Syntax: Operands: Operation: Status Affected: Description:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
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RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] RLF 0 f 127 d [0,1] See description below C The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is stored back in register 'f'.
C Register f
SLEEP Syntax: Operands: Operation: [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down STATUS bit, PD is cleared. Time-out STATUS bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped.
f,d
Status Affected: Description:
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
SUBLW Syntax: Operands: Operation: Description:
Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight-bit literal 'k'. The result is placed in the W register.
Status Affected: C, DC, Z
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
C Register f
SUBWF Syntax: Operands: Operation: Status Affected: Description:
Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) C, DC, Z Subtract (2's complement method) W register from register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
(c) 2006 Microchip Technology Inc.
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SWAPF Syntax: Operands: Operation: Status Affected: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed in register 'f'. XORWF Syntax: Operands: Operation: Status Affected: Description: Exclusive OR W with f [label] XORWF f,d 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
XORLW Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR Literal with W [label] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal 'k'. The result is placed in the W register.
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11.0 DEVELOPMENT SUPPORT
11.1
The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
(c) 2006 Microchip Technology Inc.
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11.2 MPASM Assembler 11.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
11.6 11.3 MPLAB C18 and MPLAB C30 C Compilers
MPLAB SIM Software Simulator
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 family of microcontrollers and the dsPIC30, dsPIC33 and PIC24 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
11.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
DS40039D-page 80
(c) 2006 Microchip Technology Inc.
PIC16F630/676
11.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 11.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
11.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
11.8
MPLAB ICE 4000 High-Performance In-Circuit Emulator
The MPLAB ICE 4000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high-end PIC MCUs and dsPIC DSCs. Software control of the MPLAB ICE 4000 In-Circuit Emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, and up to 2 Mb of emulation memory. The MPLAB ICE 4000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
(c) 2006 Microchip Technology Inc.
DS40039D-page 81
PIC16F630/676
11.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
11.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart(R) battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits.
11.12 PICkit 2 Development Programmer
The PICkitTM 2 Development Programmer is a low-cost programmer with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers.
DS40039D-page 82
(c) 2006 Microchip Technology Inc.
PIC16F630/676
12.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings Ambient temperature under bias........................................................................................................... -40 to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS ..................................................................................................... -0.3 to +6.5V Voltage on MCLR with respect to Vss ..................................................................................................-0.3 to +13.5V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ..................................................................................................................... 300 mA Maximum current into VDD pin ........................................................................................................................ 250 mA Input clamp current, IIK (VI < 0 or VI > VDD)............................................................................................................... 20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD)......................................................................................................... 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by PORTA and PORTC (combined) .......................................................................... 200 mA Maximum current sourced PORTA and PORTC (combined) .......................................................................... 200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL). NOTICE: Stresses above those listed under `Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than pulling this pin directly to VSS.
(c) 2006 Microchip Technology Inc.
DS40039D-page 83
PIC16F630/676
FIGURE 12-1: PIC16F630/676 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20
Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 12-2:
PIC16F676 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20
Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS40039D-page 84
(c) 2006 Microchip Technology Inc.
PIC16F630/676
FIGURE 12-3: PIC16F676 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0C TA +125C
5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.2 2.0 0 4 8 10 12 16 20
Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
(c) 2006 Microchip Technology Inc.
DS40039D-page 85
PIC16F630/676
12.1 DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions FOSC < = 4 MHz: PIC16F630/676 with A/D off PIC16F676 with A/D on, 0C to +125C PIC16F676 with A/D on, -40C to +125C 4 MHZ < FOSC < = 10 MHz Device in SLEEP mode See section on Power-on Reset for details DC CHARACTERISTICS Param No. D001 D001A D001B D001C D001D D002 D003 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal
Sym VDD
Characteristic Supply Voltage
2.0 2.2 2.5 3.0 4.5 1.5* --
-- -- -- -- -- -- VSS
5.5 5.5 5.5 5.5 5.5 -- --
V V V V V V V
D004
SVDD
0.05*
--
--
V/ms See section on Power-on Reset for details
D005
VBOD
--
2.1
--
V
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
DS40039D-page 86
(c) 2006 Microchip Technology Inc.
PIC16F630/676
12.2 DC Characteristics: PIC16F630/676-I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param No. D010 Conditions Device Characteristics Supply Current (IDD) Min -- -- -- D011 -- -- -- D012 -- -- -- D013 -- -- -- D014 -- -- -- D015 -- -- -- D016 -- -- -- D017 -- -- Typ 9 18 35 110 190 330 220 370 0.6 70 140 260 180 320 580 340 500 0.8 180 320 580 2.1 2.4 Max 16 28 54 150 280 450 280 650 1.4 110 250 390 250 470 850 450 780 1.1 250 450 800 2.95 3.0 Units VDD A A A A A A A A mA A A A A A A A A mA A A A mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator Mode FOSC = 4 MHz EXTRC Mode FOSC = 4 MHz INTOSC Mode FOSC = 4 MHz EC Oscillator Mode FOSC = 1 MHz EC Oscillator Mode FOSC = 4 MHz XT Oscillator Mode FOSC = 1 MHz XT Oscillator Mode Note FOSC = 32 kHz LP Oscillator Mode
Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption.
(c) 2006 Microchip Technology Inc.
DS40039D-page 87
PIC16F630/676
12.3 DC Characteristics: PIC16F630/676-I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param No. D020 Conditions Device Characteristics Power-down Base Current (IPD) Min -- -- -- D021 -- -- -- D022 D023 -- -- -- -- -- D024 -- -- -- D025 -- -- -- D026 -- -- Typ 0.99 1.2 2.9 0.3 1.8 8.4 58 109 3.3 6.1 11.5 58 85 138 4.0 4.6 6.0 1.2 0.0022 Max 700 770 995 1.5 3.5 17 70 130 6.5 8.5 16 70 100 160 6.5 7.0 10.5 755 1.0 Units VDD nA nA nA A A A A A A A A A A A A A A nA A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 A/D Current(1) T1 OSC Current(1) CVREF Current(1) Comparator Current(1) BOD Current(1) WDT Current(1) Note WDT, BOD, Comparators, VREF, and T1OSC disabled
Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.
DS40039D-page 88
(c) 2006 Microchip Technology Inc.
PIC16F630/676
12.4
DC Characteristics: PIC16F630/676-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Param No. D010E Conditions Device Characteristics Supply Current (IDD) Min -- -- -- D011E -- -- -- D012E -- -- -- D013E -- -- -- D014E -- -- -- D015E -- -- -- D016E -- -- -- D017E -- -- Typ 9 18 35 110 190 330 220 370 0.6 70 140 260 180 320 580 340 500 0.8 180 320 580 2.1 2.4 Max 16 28 54 150 280 450 280 650 1.4 110 250 390 250 470 850 450 780 1.1 250 450 800 2.95 3.0 Units VDD A A A A A A A A mA A A A A A A A A mA A A A mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator Mode FOSC = 4 MHz EXTRC Mode FOSC = 4 MHz INTOSC Mode FOSC = 4 MHz EC Oscillator Mode FOSC = 1 MHz EC Oscillator Mode FOSC = 4 MHz XT Oscillator Mode FOSC = 1 MHz XT Oscillator Mode Note FOSC = 32 kHz LP Oscillator Mode
Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption.
(c) 2006 Microchip Technology Inc.
DS40039D-page 89
PIC16F630/676
12.5
DC Characteristics: PIC16F630/676-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Param No. D020E Conditions Device Characteristics Power-down Base Current (IPD) Min -- -- -- D021E -- -- -- D022E D023E -- -- -- -- -- D024E -- -- -- D025E -- -- -- D026E -- -- Typ 0.00099 0.0012 0.0029 0.3 1.8 8.4 58 109 3.3 6.1 11.5 58 85 138 4.0 4.6 6.0 0.0012 0.0022 Max 3.5 4.0 8.0 6.0 9.0 20 70 130 10 13 24 70 100 165 10 12 20 6.0 8.5 Units VDD A A A A A A A A A A A A A A A A A A A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 A/D Current(1) T1 OSC Current(1) CVREF Current(1) Comparator Current(1) BOD Current(1) WDT Current(1) Note WDT, BOD, Comparators, VREF, and T1OSC disabled
Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.
DS40039D-page 90
(c) 2006 Microchip Technology Inc.
PIC16F630/676
12.6 DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions DC CHARACTERISTICS Param Sym No. VIL D030 D030A D031 D032 D033 D033A VIH D040 D040A D041 D042 D043 D043A D043B D070 IPUR
Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (RC mode) OSC1 (XT and LP modes) OSC1 (HS mode) Input High Voltage I/O ports with TTL buffer
VSS VSS VSS VSS VSS VSS
-- -- -- -- -- -- -- -- -- -- -- -- -- --
0.8 0.15 VDD 0.2 VDD 0.2 VDD 0.3 0.3 VDD
V V V V V V
4.5V VDD 5.5V Otherwise Entire range (Note 1) (Note 1)
2.0 (0.25 VDD+0.8) with Schmitt Trigger buffer 0.8 VDD MCLR 0.8 VDD OSC1 (XT and LP modes) 1.6 OSC1 (HS mode) 0.7 VDD OSC1 (RC mode) 0.9 VDD PORTA Weak Pull-up 50* Current Input Leakage Current(3) I/O ports Analog inputs VREF MCLR(2) OSC1 Output Low Voltage I/O ports OSC2/CLKOUT (RC mode) Output High Voltage I/O ports OSC2/CLKOUT (RC mode)
-- -- -- -- --
250
VDD VDD VDD VDD VDD VDD VDD 400*
V V V V V V A
4.5V VDD 5.5V otherwise entire range (Note 1) (Note 1) VDD = 5.0V, VPIN = VSS
D060 D060A D060B D061 D063
IIL
0.1 0.1 0.1 0.1 0.1
1 1 1 5 5
A A A A A
VSS VPIN VDD, Pin at hi-impedance VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD, XT, HS and LP osc configuration IOL = 8.5 mA, VDD = 4.5V (Ind.) IOL = 1.6 mA, VDD = 4.5V (Ind.) IOL = 1.2 mA, VDD = 4.5V (Ext.) IOH = -3.0 mA, VDD = 4.5V (Ind.) IOH = -1.3 mA, VDD = 4.5V (Ind.) IOH = -1.0 mA, VDD = 4.5V (Ext.)
D080 D083
VOL
-- --
-- --
0.6 0.6
V V
D090 D092
VOH
VDD - 0.7 VDD - 0.7
-- --
-- --
V V
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
(c) 2006 Microchip Technology Inc.
DS40039D-page 91
PIC16F630/676
12.7 DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended) (Cont.)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Min Typ Max Units Conditions
DC CHARACTERISTICS Param No.
Sym
D100
Capacitive Loading Specs on Output Pins COSC2 OSC2 pin
--
--
15*
pF
In XT, HS and LP modes when external clock is used to drive OSC1
D101 D120 D120A D121
CIO ED ED VDRW
All I/O pins Data EEPROM Memory Byte Endurance Byte Endurance VDD for Read/Write
-- 100K 10K VMIN
-- 1M 100K --
50* -- -- 5.5
pF E/W -40C TA +85C E/W +85C TA +125C V Using EECON to read/write VMIN = Minimum operating voltage ms Year Provided no other specifications are violated E/W -40C TA +85C
D122 D123 D124
TDEW Erase/Write cycle time TRETD Characteristic Retention TREF Number of Total Erase/Write Cycles before Refresh(1) Program FLASH Memory Cell Endurance Cell Endurance VDD for Read
-- 40 1M
5 -- 10M
6 -- --
D130 D130A D131 D132 D133 D134
EP ED VPR
10K 1K VMIN 4.5 -- 40
100K 10K -- -- 2 --
-- -- 5.5 5.5 2.5 --
VPEW VDD for Erase/Write TPEW Erase/Write cycle time TRETD Characteristic Retention
E/W -40C TA +85C E/W +85C TA +125C V VMIN = Minimum operating voltage V ms Year Provided no other specifications are violated
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: See Section 8.5.1 for additional information.
DS40039D-page 92
(c) 2006 Microchip Technology Inc.
PIC16F630/676
12.8 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid Hi-impedance
FIGURE 12-4:
LOAD CONDITIONS
Load Condition 1 VDD/2 Load Condition 2
RL
Pin VSS
RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins for OSC2 output
(c) 2006 Microchip Technology Inc.
DS40039D-page 93
PIC16F630/676
12.9 AC CHARACTERISTICS: PIC16F630/676 (INDUSTRIAL, EXTENDED)
EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 12-5:
OSC1 1 2 CLKOUT 3 3 4 4
TABLE 12-1:
Param No. Sym FOSC
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency(1) Min DC DC DC DC 5 -- DC 0.1 1 27 50 50 250 27 -- 250 250 50 Typ -- -- -- -- -- 4 -- -- -- -- -- -- -- 250 -- -- -- Max 37 4 20 20 37 -- 4 4 20 200 -- -- 10,000 1,000 Units kHz MHz MHz MHz kHz MHz MHz MHz MHz s ns ns ns s ns ns ns ns Conditions LP Osc mode XT mode HS mode EC mode LP Osc mode INTOSC mode RC Osc mode XT Osc mode HS Osc mode LP Osc mode HS Osc mode EC Osc mode XT Osc mode LP Osc mode INTOSC mode RC Osc mode XT Osc mode HS Osc mode
Oscillator Frequency(1)
1
TOSC
External CLKIN Period(1)
Oscillator Period(1)
200 TCY DC ns TCY = 4/FOSC 2* -- -- s LP oscillator, TOSC L/H duty cycle 20* -- -- ns HS oscillator, TOSC L/H duty cycle 100 * -- -- ns XT oscillator, TOSC L/H duty cycle 4 TosR, External CLKIN Rise -- -- 50* ns LP oscillator TosF External CLKIN Fall -- -- 25* ns XT oscillator -- -- 15* ns HS oscillator * These parameters are characterized but not tested. Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 3 TosL, TosH Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at `min' values with an external clock applied to OSC1 pin. When an external clock input is used, the `max' cycle time limit is `DC' (no clock) for all devices.
2
TCY
Instruction Cycle Time(1) External CLKIN (OSC1) High External CLKIN Low
DS40039D-page 94
(c) 2006 Microchip Technology Inc.
PIC16F630/676
TABLE 12-2:
Param No. F10 Sym
PRECISION INTERNAL OSCILLATOR PARAMETERS
Characteristic Freq Min Tolerance 1 2 5 3.96 3.92 3.80 Typ 4.00 4.00 4.00 Max 4.04 4.08 4.20 Units Conditions
FOSC Internal Calibrated INTOSC Frequency
F14
-- -- -- -- -- -- * These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise only and are not tested.
TIOSC Oscillator Wake-up from
ST
SLEEP start-up time*
6 4 3
8 6 5
MHz VDD = 3.5V, 25C MHz 2.5V VDD 5.5V 0C TA +85C MHz 2.0V VDD 5.5V -40C TA +85C (IND) -40C TA +125C (EXT) s VDD = 2.0V, -40C to +85C s VDD = 3.0V, -40C to +85C s VDD = 5.0V, -40C to +85C
stated. These parameters are for design guidance
(c) 2006 Microchip Technology Inc.
DS40039D-page 95
PIC16F630/676
FIGURE 12-6: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O pin (Input) 17 I/O pin (Output) Old Value 20, 21 15 New Value 19 18 22 23 12 16 Q1 Q2 11 Q3
TABLE 12-3:
Param No. 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLKOUT AND I/O TIMING REQUIREMENTS
Sym Characteristic Min -- -- -- -- -- TOSC + 200 ns 0 -- -- 100 0 -- -- 25 TCY Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 10 -- -- Max 200 200 100 100 20 -- -- 150 * 300 -- -- 40 40 -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TosH2ckL OSC1 to CLOUT TosH2ckH OSC1 to CLOUT TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time)
TioV2osH Port input valid to OSC1 (I/O in setup time) TioR TioF Tinp Trbp Port output rise time Port output fall time INT pin high or low time PORTA change INT high or low time
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4xTOSC.
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FIGURE 12-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer Reset 34 I/O Pins 32 30
31 34
FIGURE 12-8:
BROWN-OUT DETECT TIMING AND CHARACTERISTICS
VDD BVDD (Device in Brown-out Detect) (Device not in Brown-out Detect)
35
RESET (due to BOD)
72 ms time-out(1)
Note 1: 72 ms delay only if PWRTE bit in configuration word is programmed to `0'.
(c) 2006 Microchip Technology Inc.
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TABLE 12-4:
Param No. 30 31
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT DETECT REQUIREMENTS
Sym Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Detect Voltage Brown-out Hysteresis Brown-out Detect Pulse Width Min 2 11 10 10 -- 28* TBD -- 2.025 TBD 100* Typ -- 18 17 17 1024TOSC 72 TBD -- -- -- -- Max -- 24 25 30 -- 132* TBD 2.0 2.175 -- -- Units s ms ms ms -- ms ms s V -- s VDD BVDD (D005) Conditions VDD = 5V, -40C to +85C Extended temperature VDD = 5V, -40C to +85C Extended temperature TOSC = OSC1 period VDD = 5V, -40C to +85C Extended Temperature
TMCL TWDT
32 33* 34
TOST TPWRT TIOZ BVDD
35
TBOD
* These parameters are characterized but not tested. Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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(c) 2006 Microchip Technology Inc.
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FIGURE 12-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI 40 42 41
T1CKI 45 47 TMR0 or TMR1 46 48
TABLE 12-5:
Param No. 40* 41* 42* Sym Tt0H Tt0L Tt0P
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 DC 2 TOSC* Synchronous, with Prescaler Asynchronous Typ -- -- -- -- -- Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (2, 4, ..., 256) Conditions
45*
Tt1H
T1CKI High Time Synchronous, No Prescaler
-- -- -- -- -- -- --
-- -- -- -- -- -- --
ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46*
Tt1L
T1CKI Low Time
Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous
47*
Tt1P
T1CKI Input Period
Synchronous
Asynchronous Ft1 48 Timer1 oscillator input frequency range (oscillator enabled by setting bit T1OSCEN)
-- -- --
-- 200* 7 TOSC*
ns kHz --
TCKEZtmr1 Delay from external clock edge to timer increment *
These parameters are characterized but not tested. Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2006 Microchip Technology Inc.
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TABLE 12-6: COMPARATOR SPECIFICATIONS
Standard Operating Conditions -40C to +125C (unless otherwise stated) Min -- 0 +55* -- -- Typ 5.0 -- -- 150 -- Max 10 VDD - 1.5 -- 400* 10* Units mV V db ns s Comments Comparator Specifications Sym VOS VCM CMRR TRT Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time(1)
TMC2COV Comparator Mode Change to Output Valid
* These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD - 1.5V.
TABLE 12-7:
COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions -40C to +125C (unless otherwise stated) Min -- -- -- -- -- -- Typ VDD/24* VDD/32 -- -- 2k* -- Max -- -- 1/2* 1/2* -- 10* Units LSb LSb LSb LSb s Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0)
Voltage Reference Specifications Sym Characteristics Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time
(1)
* These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
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TABLE 12-8:
Param No. A01 A02 A03 A04 A05 A06 A07 A10 A20 A20A A21 A25 A30 Sym NR EABS EIL EDL EFS EOFF EGN -- VREF
PIC16F676 A/D CONVERTER CHARACTERISTICS:
Characteristic Resolution Total Absolute Error* Integral Error Differential Error Full Scale Range Offset Error Gain Error Monotonicity Reference Voltage Min -- -- -- -- 2.2* -- -- -- 2.0 2.5 VSS VSS -- Typ -- -- -- -- -- -- --
guaranteed(3)
Max 10 bits 1 1 1 5.5* 1 1 -- -- VDD + 0.3 VDD VREF 10
Units bit LSb VREF = 5.0V LSb VREF = 5.0V
Conditions
LSb No missing codes to 10 bits VREF = 5.0V V LSb VREF = 5.0V LSb VREF = 5.0V -- V Absolute minimum to ensure 10-bit accuracy V V k VSS VAIN VREF+
--
VREF VAIN ZAIN
Reference V High (VDD or VREF) Analog Input Voltage Recommended Impedance of Analog Voltage Source VREF Input Current(2)
-- -- --
A50
IREF
10 --
-- --
1000 10
A A
During VAIN acquisition. Based on differential of VHOLD to VAIN. During A/D conversion cycle.
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from External VREF or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
(c) 2006 Microchip Technology Inc.
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FIGURE 12-10: PIC16F676 A/D CONVERSION TIMING (NORMAL MODE)
1 TCY 131 130 A/D CLK A/D DATA ADRES ADIF GO SAMPLE 132 SAMPLING STOPPED 9 8 OLD_DATA 7 6 3 2 1 0 NEW_DATA 1 TCY DONE BSF ADCON0, GO 134 Q4
(TOSC/2)(1)
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 12-9:
Param No. 130 130 Sym TAD TAD
PIC16F676 A/D CONVERSION REQUIREMENTS
Characteristic A/D Clock Period A/D Internal RC Oscillator Period Conversion Time (not including Acquisition Time)(1) Acquisition Time Min 1.6 3.0* 3.0* 2.0* -- Typ -- -- 6.0 4.0 11 Max -- -- 9.0* 6.0* -- Units s s s s TAD Conditions TOSC based, VREF 3.0V TOSC based, VREF full range ADCS<1:0> = 11 (RC mode) At VDD = 2.5V At VDD = 5.0V Set GO bit to new data in A/D result register
131
TCNV
132
TACQ
(Note 2) 5*
11.5 --
-- --
s s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 4.1 mV @ 4.096V) from the last sampled voltage (as stored on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
134
TGO
Q4 to A/D Clock Start
--
TOSC/2
--
--
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See Table 7-1 for minimum conditions.
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FIGURE 12-11: PIC16F676 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO 134 Q4 130 A/D CLK A/D DATA ADRES ADIF GO SAMPLE 132 SAMPLING STOPPED 9 8 7 6 3 2 1 0 NEW_DATA 1 TCY DONE
(TOSC/2 + TCY)(1)
131
1 TCY
OLD_DATA
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 12-10: PIC16F676 A/D CONVERSION REQUIREMENTS (SLEEP MODE)
Param No. 130 130 Sym TAD TAD Characteristic A/D Clock Period A/D Internal RC Oscillator Period Conversion Time (not including Acquisition Time)(1) Acquisition Time Min 1.6 3.0* 3.0* 2.0* 131 TCNV -- Typ -- -- 6.0 4.0 11 Max -- -- 9.0* 6.0* -- Units s s s s TAD Conditions VREF 3.0V VREF full range ADCS<1:0> = 11 (RC mode) At VDD = 2.5V At VDD = 5.0V
132
TACQ
(Note 2) 5*
11.5 --
-- --
s s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 4.1 mV @ 4.096V) from the last sampled voltage (as stored on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
134
TGO
Q4 to A/D Clock Start
--
TOSC/2 + TCY
--
--
*
These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: ADRES register may be read on the following TCY cycle. 2: See Table 7-1 for minimum conditions.
(c) 2006 Microchip Technology Inc.
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NOTES:
DS40039D-page 104
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13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at 25C. 'Max' or 'min' represents (mean + 3) or (mean - 3) respectively, where is standard deviation, over the whole temperature range.
FIGURE 13-1:
TYPICAL IPD vs. VDD OVER TEMP (-40C TO +25C)
Typical Baseline IPD
6.0E-09 5.0E-09 4.0E-09
IPD (A)
-40 3.0E-09 2.0E-09 1.0E-09 0.0E+00 2 2.5 3 3.5 4 4.5 5 5.5 0 25
VDD (V)
FIGURE 13-2:
TYPICAL IPD vs. VDD OVER TEMP (+85C)
Typical Baseline IPD
3.5E-07 3.0E-07 2.5E-07
IPD (A)
2.0E-07 85 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
(c) 2006 Microchip Technology Inc.
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FIGURE 13-3: TYPICAL IPD vs. VDD OVER TEMP (+125C)
Typical Baseline IPD
4.0E-06 3.5E-06 3.0E-06
IPD (A)
2.5E-06 2.0E-06 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 125
VDD (V)
FIGURE 13-4:
MAXIMUM IPD vs. VDD OVER TEMP (-40C TO +25C)
Maximum Baseline IPD
1.0E-07 9.0E-08 8.0E-08 7.0E-08
IPD (A)
6.0E-08 5.0E-08 4.0E-08 3.0E-08 2.0E-08 1.0E-08 0.0E+00 2 2.5 3 3.5 4 4.5 5 5.5
-40 0 25
VDD (V)
DS40039D-page 106
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FIGURE 13-5: MAXIMUM IPD vs. VDD OVER TEMP (+85C)
Maximum Baseline IPD
9.0E-07 8.0E-07 7.0E-07 6.0E-07 5.0E-07 4.0E-07 3.0E-07 2.0E-07 1.0E-07 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 85
IPD (A)
VDD (V)
FIGURE 13-6:
MAXIMUM IPD vs. VDD OVER TEMP (+125C)
Maximum Baseline IPD
9.0E-06 8.0E-06 7.0E-06
IPD (A)
6.0E-06 5.0E-06 4.0E-06 3.0E-06 2.0E-06 1.0E-06 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 125
VDD (V)
(c) 2006 Microchip Technology Inc.
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FIGURE 13-7: TYPICAL IPD WITH BOD ENABLED vs. VDD OVER TEMP (-40C TO +125C)
Typical BOD IPD
130 120 110 -40
IPD (uA)
100 90 80 70 60 50 3 3.5 4 4.5 5 5.5
0 25 85 125
VDD (V)
FIGURE 13-8:
TYPICAL IPD WITH CMP ENABLED vs. VDD OVER TEMP (-40C TO +125C)
Typical Comparator IPD
1.8E-05 1.6E-05 1.4E-05 1.2E-05 -40 0 25 8.0E-06 6.0E-06 4.0E-06 2.0E-06 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 85 125
IPD (A)
1.0E-05
VDD (V)
DS40039D-page 108
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FIGURE 13-9: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (-40C TO +25C)
Typical A/D IPD
5.0E-09 4.5E-09 4.0E-09 3.5E-09 3.0E-09 2.5E-09 2.0E-09 1.5E-09 1.0E-09 5.0E-10 0.0E+00 2 2.5 3 3.5 4 4.5 5 5.5
IPD (A)
-40 0 25
VDD (V)
FIGURE 13-10:
TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+85C)
Typical A/D IPD
3.5E-07 3.0E-07 2.5E-07
IPD (A)
2.0E-07 85 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
(c) 2006 Microchip Technology Inc.
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FIGURE 13-11: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+125C)
Typical A/D IPD
3.5E-06 3.0E-06
IPD (A)
2.5E-06 2.0E-06 125 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
FIGURE 13-12:
TYPICAL IPD WITH T1 OSC ENABLED vs. VDD OVER TEMP (-40C TO +125C), 32 KHZ, C1 AND C2=50 pF)
Typical T1 IPD
1.20E-05 1.00E-05 8.00E-06 -40 0 6.00E-06 4.00E-06 2.00E-06 0.00E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 25 85 125
IPD (A)
VDD (V)
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FIGURE 13-13: TYPICAL IPD WITH CVREF ENABLED vs. VDD OVER TEMP (-40C TO +125C)
Typical CVREF IPD
160 140
IPD (uA)
120 100 80 60 40 2 2.5 3 3.5 4 4.5 5 5.5
-40 0 25 85 125
VDD (V)
FIGURE 13-14:
TYPICAL IPD WITH WDT ENABLED vs. VDD OVER TEMP (-40C TO +125C)
Typical WDT IPD
16 14 12 -40 0 25 85 125
IPD (uA)
10 8 6 4 2 0 2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
(c) 2006 Microchip Technology Inc.
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FIGURE 13-15: MAXIMUM AND MINIMUM INTOSC FREQ vs. TEMPERATURE WITH 0.1F AND 0.01F DECOUPLING (VDD = 3.5V)
Internal Oscillator Frequency vs Temperature
4.20E+06 4.15E+06
Frequency (Hz)
4.10E+06 4.05E+06 4.00E+06 3.95E+06 3.90E+06 3.85E+06 3.80E+06 -40C 0C 25C 85C 125C -3sigma average +3sigma
Temperature (C)
FIGURE 13-16:
MAXIMUM AND MINIMUM INTOSC FREQ vs. VDD WITH 0.1F AND 0.01F DECOUPLING (+25C)
Internal Oscillator Frequency vs VDD
4.20E+06
Frequency (Hz)
4.15E+06 4.10E+06 4.05E+06 4.00E+06 3.95E+06 3.90E+06 3.85E+06 3.80E+06 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V -3sigma average +3sigma
VDD (V)
DS40039D-page 112
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FIGURE 13-17: TYPICAL WDT PERIOD vs. VDD (-40C TO +125C)
WDT Time-out
50 45 40 35 30 25 20 15 10 5 0 2 2.5 3 3.5 4 4.5 5 5.5
-40 0 25 85 125
Time (mS)
V DD (V)
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NOTES:
DS40039D-page 114
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14.0
14.1
PACKAGING INFORMATION
Package Marking Information
14-Lead PDIP (Skinny DIP) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example 16F630-I e3 0215/017
14-Lead SOIC XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example 16F630-E e3 0215/017
14-Lead TSSOP XXXXXXXX YYWW NNN
Example 16F630 e3 0215 017
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2006 Microchip Technology Inc.
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14.2 Package Details
The following sections give the technical details of the packages.
14-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
E1
D
2 n 1
E A A2
c eB A1 B1 B p
L
MAX Number of Pins Pitch Top to Seating Plane A .140 .170 4.32 Molded Package Thickness A2 .115 .145 3.68 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 8.26 Molded Package Width .240 .250 .260 6.60 E1 Overall Length D .740 .750 .760 19.30 Tip to Seating Plane L .125 .130 .135 3.43 c Lead Thickness .008 .012 .015 0.38 Upper Lead Width B1 .045 .058 .070 1.78 Lower Lead Width B .014 .018 .022 0.56 Overall Row Spacing eB .310 .370 .430 10.92 Mold Draft Angle Top 5 10 15 15 Mold Draft Angle Bottom 5 10 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005
Units Dimension Limits n p
MIN
INCHES* NOM 14 .100 .155 .130
MAX
MIN
MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
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14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
E E1
p
D
2 B n 1 h 45 c A A2
L A1
MAX Number of Pins Pitch Overall Height A .053 .069 1.75 Molded Package Thickness A2 .052 .061 1.55 Standoff A1 .004 .010 0.25 Overall Width E .228 .244 6.20 Molded Package Width E1 .150 .157 3.99 Overall Length D .337 .347 8.81 Chamfer Distance h .010 .020 0.51 Foot Length L .016 .050 1.27 Foot Angle 0 8 8 c Lead Thickness .008 .010 0.25 Lead Width B .014 .020 0.51 Mold Draft Angle Top 0 15 15 Mold Draft Angle Bottom 0 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 Revised 7-20-06
Units Dimension Limits n p
MIN
INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12
MAX
MIN
MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12
(c) 2006 Microchip Technology Inc.
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14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
E E1 p
D
2 n B 1
A c
L Units Dimension Limits MIN n p A A2 A1 E E1 D L c B .039 .033 .002 .246 .169 .193 .020 0 .004 .007 INCHES NOM 14 .026 BSC .041 .035 .004 .251 .173 .197 .024 4 .006 .010 12 REF 12 REF
A1 MILLIMETERS* MAX MIN NOM 14 0.65 BSC .043 .037 .006 .256 .177 .201 .028 8 .008 .012 1.00 0.85 0.05 6.25 4.30 4.90 0.50 0 0.09 0.19 1.05 0.90 0.10 6.38 4.40 5.00 0.60 4 0.15 0.25 12 REF 12 REF
A2
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
1.10 0.95 0.15 6.50 4.50 5.10 0.70 8 0.20 0.30
* Controlling Parameter Notes: Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tole rance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MO-153 AB-1 Drawing No. C04-087
Revised: 08-17-05
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APPENDIX A:
Revision A
This is a new data sheet.
DATA SHEET REVISION HISTORY
APPENDIX B:
DEVICE DIFFERENCES
The differences between the PIC16F630/676 devices listed in this data sheet are shown in Table B-1.
Revision B
Added characterization graphs. Updated specifications. Added notes to indicate Microchip programmers maintain all calibration bits to factory settings and the PIC16F676 ANSEL register must be initialized to configure pins as digital I/O.
TABLE B-1:
Feature
DEVICE DIFFERENCES
PIC16F630 PIC16F676
A/D
No
Yes
Revision C Revision D
Updated Package Drawings; Replaced PICmicro with PIC.
(c) 2006 Microchip Technology Inc.
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APPENDIX C: DEVICE MIGRATIONS APPENDIX D:
This section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a PIC16C74A to a PIC16C74B).
Not Applicable
MIGRATING FROM OTHER PIC(R) DEVICES
This discusses some of the issues in migrating from other PIC devices to the PIC16F6XX family of devices.
D.1
PIC12C67X to PIC12F6XX FEATURE COMPARISON
PIC12C67X PIC16F6XX
TABLE 1:
Feature
Max Operating Speed Max Program Memory A/D Resolution Data EEPROM Oscillator Modes Brown-out Detect Internal Pull-ups Interrupt-on-change Comparator
Note:
10 MHz 2048 bytes 8-bit 16 bytes 5 N RA0/1/3 RA0/1/3 N
20 MHz 1024 bytes 10-bit 64 bytes 8 Y RA0/1/2/4/5 RA0/1/2/3/4/5 Y
This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device.
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(c) 2006 Microchip Technology Inc.
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INDEX A
A/D ...................................................................................... 43 Acquisition Requirements ........................................... 47 Block Diagram............................................................. 43 Calculating Acquisition Time....................................... 47 Configuration and Operation....................................... 43 Effects of a RESET ..................................................... 48 Internal Sampling Switch (Rss) Impedance ................ 47 Operation During SLEEP ............................................ 48 PIC16F675 Converter Characteristics ...................... 101 Source Impedance...................................................... 47 Summary of Registers ................................................ 48 Absolute Maximum Ratings ................................................ 83 AC Characteristics Industrial and Extended .............................................. 94 Analog Input Connection Considerations............................ 40 Analog-to-Digital Converter. See A/D Assembler MPASM Assembler..................................................... 80 Operation During SLEEP............................................ 41 Output......................................................................... 40 Reference ................................................................... 41 Response Time .......................................................... 41 Comparator Specifications................................................ 100 Comparator Voltage Reference Specifications................. 100 Configuration Bits ............................................................... 54 Configuring the Voltage Reference..................................... 41 Crystal Operation................................................................ 55 Customer Change Notification Service............................. 125 Customer Notification Service .......................................... 125 Customer Support............................................................. 125
D
Data EEPROM Memory Associated Registers/Bits........................................... 52 Code Protection.......................................................... 52 EEADR Register......................................................... 49 EECON1 Register ...................................................... 49 EECON2 Register ...................................................... 49 EEDATA Register....................................................... 49 Data Memory Organization................................................... 7 DC Characteristics Extended and Industrial.............................................. 91 Industrial ..................................................................... 86 Debugger ............................................................................ 69 Development Support ......................................................... 79 Device Differences............................................................ 119 Device Migrations ............................................................. 120 Device Overview................................................................... 5
B
Block Diagram TMR0/WDT Prescaler................................................. 29 Block Diagrams Analog Input Mode...................................................... 40 Analog Input Model ..................................................... 47 Comparator Output ..................................................... 40 Comparator Voltage Reference .................................. 41 On-Chip Reset Circuit ................................................. 57 RA0 and RA1 Pins ...................................................... 22 RA2 ............................................................................. 23 RA3 ............................................................................. 23 RA4 ............................................................................. 24 RA5 ............................................................................. 24 RC Oscillator Mode..................................................... 56 RC0/RC1/RC2/RC3 Pins ............................................ 26 RC4 AND RC5 Pins .................................................... 26 Timer1......................................................................... 32 Watchdog Timer.......................................................... 67 Brown-out Associated Registers .................................................. 60 Brown-out Detect (BOD) ..................................................... 59 Brown-out Detect Timing and Characteristics..................... 97
E
EEPROM Data Memory Reading ...................................................................... 51 Spurious Write ............................................................ 51 Write Verify ................................................................. 51 Writing ........................................................................ 51 Electrical Specifications ...................................................... 83 Errata .................................................................................... 3
F
Firmware Instructions ......................................................... 71
G
General Purpose Register File ............................................. 7
I
ID Locations........................................................................ 69 In-Circuit Serial Programming............................................. 69 Indirect Addressing, INDF and FSR Registers ................... 18 Instruction Format............................................................... 71 Instruction Set..................................................................... 71 ADDLW....................................................................... 73 ADDWF ...................................................................... 73 ANDLW....................................................................... 73 ANDWF ...................................................................... 73 BCF ............................................................................ 73 BSF............................................................................. 73 BTFSC........................................................................ 73 BTFSS ........................................................................ 73 CALL........................................................................... 74 CLRF .......................................................................... 74 CLRW ......................................................................... 74 CLRWDT .................................................................... 74 COMF ......................................................................... 74 DECF.......................................................................... 74 DECFSZ ..................................................................... 75 GOTO ......................................................................... 75 INCF ........................................................................... 75
C
C Compilers MPLAB C18 ................................................................ 80 MPLAB C30 ................................................................ 80 Calibrated Internal RC Frequencies.................................... 95 CLKOUT ............................................................................. 56 Code Examples Changing Prescaler .................................................... 31 Data EEPROM Read .................................................. 51 Data EEPROM Write .................................................. 51 Initializing PORTA....................................................... 19 Initializing PORTC....................................................... 26 Saving STATUS and W Registers in RAM ................. 66 Write Verify ................................................................. 51 Code Protection .................................................................. 69 Comparator ......................................................................... 37 Associated Registers .................................................. 42 Configuration............................................................... 39 Effects of a RESET ..................................................... 41 I/O Operating Modes................................................... 39 Interrupts..................................................................... 42 Operation .................................................................... 38
(c) 2006 Microchip Technology Inc.
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PIC16F630/676
INCFSZ ....................................................................... 75 IORLW ........................................................................ 75 IORWF ........................................................................ 75 MOVF.......................................................................... 76 MOVLW ...................................................................... 76 MOVWF ...................................................................... 76 NOP ............................................................................ 76 RETFIE ....................................................................... 76 RETLW ....................................................................... 76 RETURN ..................................................................... 77 RLF ............................................................................. 77 RRF............................................................................. 77 SLEEP ........................................................................ 77 SUBLW ....................................................................... 77 SUBWF ....................................................................... 77 SWAPF ....................................................................... 78 XORLW ....................................................................... 78 XORWF....................................................................... 78 Summary Table........................................................... 72 Internal 4 MHz Oscillator..................................................... 56 Internal Sampling Switch (Rss) Impedance ........................ 47 Internet Address................................................................ 125 Interrupts ............................................................................. 63 A/D Converter ............................................................. 65 Comparator ................................................................. 65 Context Saving............................................................ 66 PORTA........................................................................ 65 RA2/INT ...................................................................... 65 Summary of Registers ................................................ 66 TMR0 .......................................................................... 65 Pin Descriptions and Diagrams .................................. 22 PORTA and TRISIO Registers ........................................... 19 PORTC ............................................................................... 26 Associated Registers .................................................. 27 Power Control/Status Register (PCON).............................. 59 Power-Down Mode (SLEEP) .............................................. 68 Power-on Reset (POR)....................................................... 58 Power-up Timer (PWRT) .................................................... 58 Prescaler............................................................................. 31 Switching Prescaler Assignment ................................ 31 Program Memory Organization............................................. 7 Programming, Device Instructions...................................... 71
R
RC Oscillator....................................................................... 56 Reader Response............................................................. 126 READ-MODIFY-WRITE OPERATIONS ............................. 71 Registers ADCON0 (A/D Control)............................................... 45 ADCON1..................................................................... 45 CMCON (Comparator Control) ................................... 37 CONFIG (Configuration Word) ................................... 54 EEADR (EEPROM Address) ...................................... 49 EECON1 (EEPROM Control) ..................................... 50 EEDAT (EEPROM Data) ............................................ 49 INTCON (Interrupt Control)......................................... 13 IOCA (Interrupt-on-Change PORTA).......................... 21 Maps PIC16F630 ........................................................... 8 PIC16F676 ........................................................... 8 OPTION_REG (Option) ........................................ 12, 30 OSCCAL (Oscillator Calibration) ................................ 16 PCON (Power Control) ............................................... 16 PIE1 (Peripheral Interrupt Enable 1)........................... 14 PIR1 (Peripheral Interrupt 1)....................................... 15 PORTC ....................................................................... 27 STATUS ..................................................................... 11 T1CON (Timer1 Control) ............................................ 34 TRISC......................................................................... 27 VRCON (Voltage Reference Control) ......................... 42 WPUA (Weak Pull-up PORTA)................................... 20 RESET................................................................................ 57 Revision History................................................................ 119
M
MCLR .................................................................................. 58 Memory Organization Data EEPROM Memory.............................................. 49 Microchip Internet Web Site .............................................. 125 Migrating from other PICmicro Devices ............................ 120 MPLAB ASM30 Assembler, Linker, Librarian ..................... 80 MPLAB ICD 2 In-Circuit Debugger...................................... 81 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ............................................................. 81 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator ............................................................. 81 MPLAB Integrated Development Environment Software .... 79 MPLAB PM3 Device Programmer....................................... 81 MPLINK Object Linker/MPLIB Object Librarian .................. 80
S
Software Simulator (MPLAB SIM) ...................................... 80 Special Features of the CPU .............................................. 53 Special Function Registers ................................................... 8
O
OPCODE Field Descriptions ............................................... 71 Oscillator Configurations ..................................................... 55 Oscillator Start-up Timer (OST) .......................................... 58
T
Time-out Sequence ............................................................ 59 Timer0................................................................................. 29 Associated Registers .................................................. 31 External Clock............................................................. 30 Interrupt ...................................................................... 29 Operation .................................................................... 29 T0CKI ......................................................................... 30 Timer1 Associated Registers .................................................. 35 Asynchronous Counter Mode ..................................... 35 Reading and Writing ........................................... 35 Interrupt ...................................................................... 33 Modes of Operations .................................................. 33 Operation During SLEEP............................................ 35 Oscillator..................................................................... 35 Prescaler .................................................................... 33 Timer1 Module with Gate Control ....................................... 32 Timing Diagrams
P
Packaging ......................................................................... 115 Details ....................................................................... 116 Marking ..................................................................... 115 PCL and PCLATH ............................................................... 17 Computed GOTO ........................................................ 17 Stack ........................................................................... 17 PICSTART Plus Development Programmer ....................... 82 Pinout Descriptions PIC16F630 .................................................................... 6 PIC16F676 .................................................................... 6 PORTA Additional Pin Functions ............................................. 19 Interrupt-on-Change............................................ 20 Weak Pull-up....................................................... 19 Associated Registers .................................................. 25
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(c) 2006 Microchip Technology Inc.
PIC16F630/676
CLKOUT and I/O......................................................... 96 External Clock............................................................. 94 INT Pin Interrupt.......................................................... 65 PIC16F675 A/D Conversion (Normal Mode)............. 102 PIC16F675 A/D Conversion Timing (SLEEP Mode). 103 RESET, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ......................................... 97 Time-out Sequence on Power-up (MCLR not Tied to VDD)/ Case 1 ................................................................ 62 Case 2 ................................................................ 62 Time-out Sequence on Power-up (MCLR Tied to VDD).................................................... 62 Timer0 and Timer1 External Clock ............................. 99 Timer1 Incrementing Edge.......................................... 33 Timing Parameter Symbology............................................. 93 TRISIO Registers................................................................ 19
V
Voltage Reference Accuracy/Error ..................................... 41
W
Watchdog Timer Summary of Registers ................................................ 67 Watchdog Timer (WDT) ...................................................... 66 WWW Address.................................................................. 125 WWW, On-Line Support ....................................................... 3
(c) 2006 Microchip Technology Inc.
DS40039D-page 123
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NOTES:
DS40039D-page 124
(c) 2006 Microchip Technology Inc.
PIC16F630/676
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
(c) 2006 Microchip Technology Inc.
DS40039D-page 125
PIC16F630/676
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16F630/676 Questions: 1. What are the best features of this document? Y N Literature Number: DS40039D FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS40039D-page 126
(c) 2006 Microchip Technology Inc.
PIC16F630/676
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b)
Device: : Standard VDD range T: (Tape and Reel) PIC16F630 - E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301
PIC16F676 - I/SO = Industrial Temp., SOIC
package, 20 MHz
Temperature Range:
I E
= =
-40C to +85C -40C to +125C
Package:
P SN ST
= = =
PDIP SOIC (Gull wing, 150 mil body) TSSOP(4.4 mm)
Pattern:
3-Digit Pattern Code for QTP (blank otherwise)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type.
(c) 2006 Microchip Technology Inc.
DS40039D-page 127
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-3910 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
08/29/06
DS40039D-page 128
(c) 2006 Microchip Technology Inc.

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